Patchwork [U-Boot,v2,10/10] spi: zynq_qspi: Enable READ_CMD_FULL and WRITE_CMD_FULL

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Submitter Jagannadha Sutradharudu Teki
Date Aug. 7, 2013, 8:09 p.m.
Message ID <ed9105f5-6796-4f0a-8138-b1684e64f678@VA3EHSMHS009.ehs.local>
Download mbox | patch
Permalink /patch/265607/
State Superseded
Delegated to: Jagannadha Sutradharudu Teki
Headers show

Comments

Jagannadha Sutradharudu Teki - Aug. 7, 2013, 8:09 p.m.
Zynq controller supports all basic, extended read and quad
read/write commands, so enable them in the driver so-that
the sf will look for the fastest cmd w.r.t flash supported one.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
---
Changes for v2:
	- none

 drivers/spi/zynq_qspi.c | 3 +++
 1 file changed, 3 insertions(+)

Patch

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 02a1a80..6a33719 100644
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -10,6 +10,7 @@ 
 #include <common.h>
 #include <malloc.h>
 #include <spi.h>
+#include <spi_flash.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
@@ -324,6 +325,8 @@  struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		return NULL;
 	}
 
+	zslave->slave.rd_cmd = READ_CMD_FULL;
+	zslave->slave.wr_cmd = WRITE_CMD_FULL;
 	zslave->base = (struct zynq_qspi_regs *)ZYNQ_QSPI_BASEADDR;
 	zslave->mode = mode;
 	zslave->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;