diff mbox

[2/2] powerpc: Add 2.06 tlbie mnemonics

Message ID 20090428124503.70AF1123B3@localhost.localdomain (mailing list archive)
State Superseded, archived
Headers show

Commit Message

Michael Neuling April 28, 2009, 12:45 p.m. UTC 
From: Milton Miller <miltonm@bga.com>

This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.

Only useful for bare metal systems.  

Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
---

 arch/powerpc/include/asm/mmu.h        |    5 +++++
 arch/powerpc/include/asm/ppc-opcode.h |    4 ++++
 arch/powerpc/kernel/cputable.c        |    6 ++++--
 arch/powerpc/mm/hash_native_64.c      |   13 +++++++++++--
 4 files changed, 24 insertions(+), 4 deletions(-)

Comments

Kumar Gala April 28, 2009, 1:21 p.m. UTC | #1 
On Apr 28, 2009, at 7:45 AM, Michael Neuling wrote:

> Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
> ===================================================================
> --- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
> +++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
> @@ -58,6 +58,11 @@
>  */
> #define MMU_FTR_TLBILX_EARLY_OPCODE	ASM_CONST(0x00400000)
>
> +/* This indicates that the processor uses the ISA 2.06 server tlbie
> + * mnemonics
> + */
> +#define MMU_FTR_TLBIE_206		ASM_CONST(0x00800000)
> +
> #ifndef __ASSEMBLY__
> #include <asm/cputable.h>

You aren't going to like me, but I just got rid of  
MMU_FTR_TLBILX_EARLY_OPCODE and thus freed up 0x00400000.  So a) patch  
will probably bitch when being applied by Ben b) we should use  
0x00400000.

(suggest pulling in paulus/merge as that has the "revert" patch that  
removes MMU_FTR_TLBILX_EARLY_OPCODE - and paul's sent a pull request  
to linus for it.)

- k
Michael Neuling April 29, 2009, 12:16 a.m. UTC | #2 
> > Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
> > ===================================================================
> > --- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
> > +++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
> > @@ -58,6 +58,11 @@
> >  */
> > #define MMU_FTR_TLBILX_EARLY_OPCODE	ASM_CONST(0x00400000)
> >
> > +/* This indicates that the processor uses the ISA 2.06 server tlbie
> > + * mnemonics
> > + */
> > +#define MMU_FTR_TLBIE_206		ASM_CONST(0x00800000)
> > +
> > #ifndef __ASSEMBLY__
> > #include <asm/cputable.h>
> 
> You aren't going to like me, but I just got rid of  
> MMU_FTR_TLBILX_EARLY_OPCODE and thus freed up 0x00400000.  So a) patch  
> will probably bitch when being applied by Ben b) we should use  
> 0x00400000.

Kuuuuumaaaaar!!!! :-)

> (suggest pulling in paulus/merge as that has the "revert" patch that  
> removes MMU_FTR_TLBILX_EARLY_OPCODE - and paul's sent a pull request  
> to linus for it.)

OK, new patches coming.

Mikey
Michael Neuling April 29, 2009, 12:26 a.m. UTC | #3 
These patches implement the PowerPC ISA 2.06 tlbie mnemonics

Signed-off-by: Michael Neuling <mikey@neuling.org>
--- 
Moves MMU_FTR_TLBIE_206 down one bit as the item before has now been
removed.  Thanks to Kumar for noticing.
diff mbox

Patch

Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -58,6 +58,11 @@ 
  */
 #define MMU_FTR_TLBILX_EARLY_OPCODE	ASM_CONST(0x00400000)
 
+/* This indicates that the processor uses the ISA 2.06 server tlbie
+ * mnemonics
+ */
+#define MMU_FTR_TLBIE_206		ASM_CONST(0x00800000)
+
 #ifndef __ASSEMBLY__
 #include <asm/cputable.h>
 
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -46,10 +46,12 @@ 
 #define PPC_INST_TLBILX			0x7c000024
 #define PPC_INST_TLBILX_EARLY		0x7c000626
 #define PPC_INST_WAIT			0x7c00007c
+#define PPC_INST_TLBIE			0x7c000264
 
 /* macros to insert fields into opcodes */
 #define __PPC_RA(a)	((a & 0x1f) << 16)
 #define __PPC_RB(b)	((b & 0x1f) << 11)
+#define __PPC_RS(s)	((s & 0x1f) << 21)
 #define __PPC_T_TLB(t)	((t & 0x3) << 21)
 #define __PPC_WC(w)	((w & 0x3) << 21)
 
@@ -78,5 +80,7 @@ 
 #define PPC_TLBILX_VA_EARLY(a, b)	PPC_TLBILX_EARLY(3, a, b)
 #define PPC_WAIT(w)		stringify_in_c(.long PPC_INST_WAIT | \
 					__PPC_WC(w))
+#define PPC_TLBIE(lp,a) 	stringify_in_c(.long PPC_INST_TLBIE | \
+					       __PPC_RB(a) | __PPC_RS(lp))
 
 #endif /* _ASM_POWERPC_PPC_OPCODE_H */
Index: linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/cputable.c
+++ linux-2.6-ozlabs/arch/powerpc/kernel/cputable.c
@@ -425,7 +425,8 @@  static struct cpu_spec __initdata cpu_sp
 		.cpu_name		= "POWER7 (architected)",
 		.cpu_features		= CPU_FTRS_POWER7,
 		.cpu_user_features	= COMMON_USER_POWER7,
-		.mmu_features		= MMU_FTR_HPTE_TABLE,
+		.mmu_features		= MMU_FTR_HPTE_TABLE |
+			MMU_FTR_TLBIE_206,
 		.icache_bsize		= 128,
 		.dcache_bsize		= 128,
 		.machine_check		= machine_check_generic,
@@ -438,7 +439,8 @@  static struct cpu_spec __initdata cpu_sp
 		.cpu_name		= "POWER7 (raw)",
 		.cpu_features		= CPU_FTRS_POWER7,
 		.cpu_user_features	= COMMON_USER_POWER7,
-		.mmu_features		= MMU_FTR_HPTE_TABLE,
+		.mmu_features		= MMU_FTR_HPTE_TABLE |
+			MMU_FTR_TLBIE_206,
 		.icache_bsize		= 128,
 		.dcache_bsize		= 128,
 		.num_pmcs		= 6,
Index: linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
===================================================================
--- linux-2.6-ozlabs.orig/arch/powerpc/mm/hash_native_64.c
+++ linux-2.6-ozlabs/arch/powerpc/mm/hash_native_64.c
@@ -27,6 +27,7 @@ 
 #include <asm/cputable.h>
 #include <asm/udbg.h>
 #include <asm/kexec.h>
+#include <asm/ppc-opcode.h>
 
 #ifdef DEBUG_LOW
 #define DBG_LOW(fmt...) udbg_printf(fmt)
@@ -49,14 +50,21 @@  static inline void __tlbie(unsigned long
 	case MMU_PAGE_4K:
 		va &= ~0xffful;
 		va |= ssize << 8;
-		asm volatile("tlbie %0,0" : : "r" (va) : "memory");
+ 		asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0),
+					       %2)
+			     : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+			     : "memory");
 		break;
 	default:
 		penc = mmu_psize_defs[psize].penc;
 		va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
 		va |= penc << 12;
 		va |= ssize << 8;
-		asm volatile("tlbie %0,1" : : "r" (va) : "memory");
+		va |= 1; /* L */
+ 		asm volatile(ASM_MMU_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0),
+					       %2)
+			     : : "r" (va), "r"(0), "i" (MMU_FTR_TLBIE_206)
+			     : "memory");
 		break;
 	}
 }
@@ -80,6 +88,7 @@  static inline void __tlbiel(unsigned lon
 		va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
 		va |= penc << 12;
 		va |= ssize << 8;
+		va |= 1; /* L */
 		asm volatile(".long 0x7c000224 | (%0 << 11) | (1 << 21)"
 			     : : "r"(va) : "memory");
 		break;