From patchwork Tue Aug 6 14:10:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin Liang See X-Patchwork-Id: 265063 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id A6B992C0040 for ; Wed, 7 Aug 2013 00:26:39 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4A2724A048; Tue, 6 Aug 2013 16:26:38 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jbkyPSgmP7+f; Tue, 6 Aug 2013 16:26:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 33E7F4A02D; Tue, 6 Aug 2013 16:26:33 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1FA714A02D for ; Tue, 6 Aug 2013 16:26:30 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Bd6Jt4A1kvN9 for ; Tue, 6 Aug 2013 16:26:25 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from co1outboundpool.messaging.microsoft.com (co1ehsobe005.messaging.microsoft.com [216.32.180.188]) by theia.denx.de (Postfix) with ESMTPS id 0908F4A029 for ; Tue, 6 Aug 2013 16:26:19 +0200 (CEST) Received: from mail13-co1-R.bigfish.com (10.243.78.233) by CO1EHSOBE034.bigfish.com (10.243.66.99) with Microsoft SMTP Server id 14.1.225.22; Tue, 6 Aug 2013 14:11:02 +0000 Received: from mail13-co1 (localhost [127.0.0.1]) by mail13-co1-R.bigfish.com (Postfix) with ESMTP id A3961A4020B; Tue, 6 Aug 2013 14:11:02 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(z551biz154dIzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz8275ch1de098h8275bh1de097hz2fh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h14ddh1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dc1h1dfeh1dffh1e1dh1e23h1155h) Received-SPF: pass (mail13-co1: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=clsee@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail13-co1 (localhost.localdomain [127.0.0.1]) by mail13-co1 (MessageSwitch) id 1375798260633029_31884; Tue, 6 Aug 2013 14:11:00 +0000 (UTC) Received: from CO1EHSMHS006.bigfish.com (unknown [10.243.78.241]) by mail13-co1.bigfish.com (Postfix) with ESMTP id 96B7E1C0047; Tue, 6 Aug 2013 14:11:00 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO1EHSMHS006.bigfish.com (10.243.66.16) with Microsoft SMTP Server (TLS) id 14.16.227.3; Tue, 6 Aug 2013 14:11:00 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Tue, 6 Aug 2013 07:00:19 -0700 Received: from clsee-VirtualBox.altera.com (tx-clsee-530.altera.priv.altera.com [137.57.188.103]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with ESMTP id r76EArP0001407; Tue, 6 Aug 2013 07:10:58 -0700 (PDT) From: Chin Liang See To: ZY - u-boot Date: Tue, 6 Aug 2013 09:10:47 -0500 Message-ID: <1375798247-15258-1-git-send-email-clsee@altera.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: altera.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: Machek , Chin Liang See , Pavel@theia.denx.de, Tom Rini Subject: [U-Boot] [RESEND PATCH v5 2/2] socfpga: Adding pin mux handoff files X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Adding the generated pin mux configuration by Preloader Generator tool Signed-off-by: Chin Liang See Reviewed-by: Pavel Machek Cc: Wolfgang Denk CC: Pavel Machek Cc: Dinh Nguyen Cc: Tom Rini Cc: Albert Aribaud Acked-by: Dinh Nguyen --- Changes for v2: - Fixed the word wrap issue within patch Changes for v3: - Fixed the long subject of the patch Changes for v4: - Added change log for each revision change Changes for v5: - Updated the license header for reset_manager.c - Updated the subject --- board/altera/socfpga/pinmux_config.c | 214 ++++++++++++++++++++++++++++++++++ board/altera/socfpga/pinmux_config.h | 54 +++++++++ 2 files changed, 268 insertions(+) create mode 100644 board/altera/socfpga/pinmux_config.c create mode 100644 board/altera/socfpga/pinmux_config.h diff --git a/board/altera/socfpga/pinmux_config.c b/board/altera/socfpga/pinmux_config.c new file mode 100644 index 0000000..8b09005 --- /dev/null +++ b/board/altera/socfpga/pinmux_config.c @@ -0,0 +1,214 @@ +/* This file is generated by Preloader Generator */ + +#include "pinmux_config.h" + +/* pin mux configuration data */ +unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { + 0, /* EMACIO0 - Unused */ + 2, /* EMACIO1 - USB */ + 2, /* EMACIO2 - USB */ + 2, /* EMACIO3 - USB */ + 2, /* EMACIO4 - USB */ + 2, /* EMACIO5 - USB */ + 2, /* EMACIO6 - USB */ + 2, /* EMACIO7 - USB */ + 2, /* EMACIO8 - USB */ + 0, /* EMACIO9 - Unused */ + 2, /* EMACIO10 - USB */ + 2, /* EMACIO11 - USB */ + 2, /* EMACIO12 - USB */ + 2, /* EMACIO13 - USB */ + 0, /* EMACIO14 - N/A */ + 0, /* EMACIO15 - N/A */ + 0, /* EMACIO16 - N/A */ + 0, /* EMACIO17 - N/A */ + 0, /* EMACIO18 - N/A */ + 0, /* EMACIO19 - N/A */ + 3, /* FLASHIO0 - SDMMC */ + 3, /* FLASHIO1 - SDMMC */ + 3, /* FLASHIO2 - SDMMC */ + 3, /* FLASHIO3 - SDMMC */ + 0, /* FLASHIO4 - SDMMC */ + 0, /* FLASHIO5 - SDMMC */ + 0, /* FLASHIO6 - SDMMC */ + 0, /* FLASHIO7 - SDMMC */ + 0, /* FLASHIO8 - SDMMC */ + 3, /* FLASHIO9 - SDMMC */ + 3, /* FLASHIO10 - SDMMC */ + 3, /* FLASHIO11 - SDMMC */ + 3, /* GENERALIO0 - TRACE */ + 3, /* GENERALIO1 - TRACE */ + 3, /* GENERALIO2 - TRACE */ + 3, /* GENERALIO3 - TRACE */ + 3, /* GENERALIO4 - TRACE */ + 3, /* GENERALIO5 - TRACE */ + 3, /* GENERALIO6 - TRACE */ + 3, /* GENERALIO7 - TRACE */ + 3, /* GENERALIO8 - TRACE */ + 3, /* GENERALIO9 - SPIM0 */ + 3, /* GENERALIO10 - SPIM0 */ + 3, /* GENERALIO11 - SPIM0 */ + 3, /* GENERALIO12 - SPIM0 */ + 2, /* GENERALIO13 - CAN0 */ + 2, /* GENERALIO14 - CAN0 */ + 3, /* GENERALIO15 - I2C0 */ + 3, /* GENERALIO16 - I2C0 */ + 2, /* GENERALIO17 - UART0 */ + 2, /* GENERALIO18 - UART0 */ + 0, /* GENERALIO19 - N/A */ + 0, /* GENERALIO20 - N/A */ + 0, /* GENERALIO21 - N/A */ + 0, /* GENERALIO22 - N/A */ + 0, /* GENERALIO23 - N/A */ + 0, /* GENERALIO24 - N/A */ + 0, /* GENERALIO25 - N/A */ + 0, /* GENERALIO26 - N/A */ + 0, /* GENERALIO27 - N/A */ + 0, /* GENERALIO28 - N/A */ + 0, /* GENERALIO29 - N/A */ + 0, /* GENERALIO30 - N/A */ + 0, /* GENERALIO31 - N/A */ + 2, /* MIXED1IO0 - EMAC */ + 2, /* MIXED1IO1 - EMAC */ + 2, /* MIXED1IO2 - EMAC */ + 2, /* MIXED1IO3 - EMAC */ + 2, /* MIXED1IO4 - EMAC */ + 2, /* MIXED1IO5 - EMAC */ + 2, /* MIXED1IO6 - EMAC */ + 2, /* MIXED1IO7 - EMAC */ + 2, /* MIXED1IO8 - EMAC */ + 2, /* MIXED1IO9 - EMAC */ + 2, /* MIXED1IO10 - EMAC */ + 2, /* MIXED1IO11 - EMAC */ + 2, /* MIXED1IO12 - EMAC */ + 2, /* MIXED1IO13 - EMAC */ + 0, /* MIXED1IO14 - Unused */ + 3, /* MIXED1IO15 - QSPI */ + 3, /* MIXED1IO16 - QSPI */ + 3, /* MIXED1IO17 - QSPI */ + 3, /* MIXED1IO18 - QSPI */ + 3, /* MIXED1IO19 - QSPI */ + 3, /* MIXED1IO20 - QSPI */ + 0, /* MIXED1IO21 - GPIO */ + 0, /* MIXED2IO0 - N/A */ + 0, /* MIXED2IO1 - N/A */ + 0, /* MIXED2IO2 - N/A */ + 0, /* MIXED2IO3 - N/A */ + 0, /* MIXED2IO4 - N/A */ + 0, /* MIXED2IO5 - N/A */ + 0, /* MIXED2IO6 - N/A */ + 0, /* MIXED2IO7 - N/A */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; diff --git a/board/altera/socfpga/pinmux_config.h b/board/altera/socfpga/pinmux_config.h new file mode 100644 index 0000000..f278f2b --- /dev/null +++ b/board/altera/socfpga/pinmux_config.h @@ -0,0 +1,54 @@ +/* This file is generated by Preloader Generator */ + +#ifndef _PRELOADER_PINMUX_CONFIG_H_ +#define _PRELOADER_PINMUX_CONFIG_H_ + +/* + * State of enabling for which IP connected out through the muxing. + * Value 1 mean the IP connection is muxed out + */ +#define CONFIG_HPS_EMAC0 (0) +#define CONFIG_HPS_EMAC1 (1) +#define CONFIG_HPS_USB0 (0) +#define CONFIG_HPS_USB1 (1) +#define CONFIG_HPS_NAND (0) +#define CONFIG_HPS_SDMMC (1) +#define CONFIG_HPS_QSPI (1) +#define CONFIG_HPS_UART0 (1) +#define CONFIG_HPS_UART1 (0) +#define CONFIG_HPS_TRACE (1) +#define CONFIG_HPS_I2C0 (1) +#define CONFIG_HPS_I2C1 (0) +#define CONFIG_HPS_I2C2 (0) +#define CONFIG_HPS_I2C3 (0) +#define CONFIG_HPS_SPIM0 (1) +#define CONFIG_HPS_SPIM1 (0) +#define CONFIG_HPS_SPIS0 (0) +#define CONFIG_HPS_SPIS1 (0) +#define CONFIG_HPS_CAN0 (1) +#define CONFIG_HPS_CAN1 (0) + +/* IP attribute value (which affected by pin muxing configuration) */ +#define CONFIG_HPS_SDMMC_BUSWIDTH (4) + +/* 1 if the pins are connected out */ +#define CONFIG_HPS_QSPI_CS0 (1) +#define CONFIG_HPS_QSPI_CS1 (0) +#define CONFIG_HPS_QSPI_CS2 (0) +#define CONFIG_HPS_QSPI_CS3 (0) + +/* UART */ +/* 1 means the pin is mux out or available */ +#define CONFIG_HPS_UART0_TX (1) +#define CONFIG_HPS_UART0_RX (1) +#define CONFIG_HPS_UART0_CTS (0) +#define CONFIG_HPS_UART0_RTS (0) +#define CONFIG_HPS_UART1_TX (0) +#define CONFIG_HPS_UART1_RX (0) +#define CONFIG_HPS_UART1_CTS (0) +#define CONFIG_HPS_UART1_RTS (0) + +/* Pin mux data */ +#define CONFIG_HPS_PINMUX_NUM (207) + +#endif /* _PRELOADER_PINMUX_CONFIG_H_ */