Patchwork [U-Boot,RESEND,v5,1/1] socfpga: Adding configuration for development kit

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Submitter Chin Liang See
Date Aug. 6, 2013, 2:08 p.m.
Message ID <1375798115-15124-1-git-send-email-clsee@altera.com>
Download mbox | patch
Permalink /patch/265061/
State Superseded
Delegated to: Albert ARIBAUD
Headers show

Comments

Chin Liang See - Aug. 6, 2013, 2:08 p.m.
Separating the configuration file for Virtual
Target and real hardware Cyclone V development kit

Signed-off-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Pavel Machek
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
---
Changes for v2:
   - Fixed the word wrap issue within patch
Changes for v3:
   - Fixed the long subject of the patch
Changes for v4:
   - Added change log for each revision change
Changes for v5:
   - Added Reviewed-by: Pavel Machek
   - Cc: Tom Rini
---
 include/configs/socfpga_cyclone5.h |   28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)
dinguyen@altera.com - Aug. 6, 2013, 4 p.m.
On Tue, 2013-08-06 at 09:08 -0500, Chin Liang See wrote:
> Separating the configuration file for Virtual
> Target and real hardware Cyclone V development kit
> 
> Signed-off-by: Chin Liang See <clsee@altera.com>
> Reviewed-by: Pavel Machek

Include Pavel's email address.

> Cc: Wolfgang Denk <wd@denx.de>
> CC: Pavel Machek <pavel@denx.de>
> Cc: Dinh Nguyen <dinguyen@altera.com>
> Cc: Tom Rini <trini@ti.com>
> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> ---
> Changes for v2:
>    - Fixed the word wrap issue within patch
> Changes for v3:
>    - Fixed the long subject of the patch
> Changes for v4:
>    - Added change log for each revision change
> Changes for v5:
>    - Added Reviewed-by: Pavel Machek
>    - Cc: Tom Rini

Re-org this to have the latest, v5 at the top.

> ---
>  include/configs/socfpga_cyclone5.h |   28 +++++++++++++++++++++-------
>  1 file changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
> index b5a7a9a..06aeba6 100644
> --- a/include/configs/socfpga_cyclone5.h
> +++ b/include/configs/socfpga_cyclone5.h
> @@ -11,6 +11,8 @@
>  /*
>   * High level configuration
>   */
> +/* Virtual target or real hardware */
> +#define CONFIG_SOCFPGA_VIRTUAL_TARGET
>  
>  #define CONFIG_ARMV7
>  #define CONFIG_L2_OFF
> @@ -21,11 +23,12 @@
>  #define CONFIG_SINGLE_BOOTLOADER
>  #define CONFIG_SOCFPGA
>  
> +/* base address for .text section */
> +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>  #define CONFIG_SYS_TEXT_BASE		0x08000040
> -#define V_NS16550_CLK			1000000
> -#define CONFIG_BAUDRATE			57600
> -#define CONFIG_SYS_HZ			1000
> -#define CONFIG_TIMER_CLOCK_KHZ		2400
> +#else
> +#define CONFIG_SYS_TEXT_BASE		0x01000040
> +#endif
>  #define CONFIG_SYS_LOAD_ADDR		0x7fc0
>  
>  /* Console I/O Buffer Size */
> @@ -154,7 +157,7 @@
>  /* SDRAM Bank #1 */
>  #define CONFIG_SYS_SDRAM_BASE		0x00000000
>  /* SDRAM memory size */
> -#define PHYS_SDRAM_1_SIZE		0x80000000
> +#define PHYS_SDRAM_1_SIZE		0x40000000
>  
>  #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
>  #define CONFIG_SYS_MEMTEST_START	0x00000000
> @@ -170,8 +173,13 @@
>  #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
>  #define CONFIG_CONS_INDEX               1
>  #define CONFIG_SYS_NS16550_COM1		UART0_BASE
> -
>  #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
> +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
> +#define V_NS16550_CLK			1000000
> +#else
> +#define V_NS16550_CLK			100000000
> +#endif
> +#define CONFIG_BAUDRATE			115200
>  
>  /*
>   * FLASH
> @@ -184,9 +192,15 @@
>  /* This timer use eosc1 where the clock frequency is fixed
>   * throughout any condition */
>  #define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
> -
>  /* reload value when timer count to zero */
>  #define TIMER_LOAD_VAL			0xFFFFFFFF
> +/* Timer info */
> +#define CONFIG_SYS_HZ			1000
> +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
> +#define CONFIG_TIMER_CLOCK_KHZ		2400
> +#else
> +#define CONFIG_TIMER_CLOCK_KHZ		25000
> +#endif
>  
>  #define CONFIG_ENV_IS_NOWHERE
>
Chin Liang See - Aug. 7, 2013, 3:03 p.m.
On Tue, 2013-08-06 at 11:00 -0500, Dinh Nguyen wrote:
> On Tue, 2013-08-06 at 09:08 -0500, Chin Liang See wrote:
> > Separating the configuration file for Virtual
> > Target and real hardware Cyclone V development kit
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Reviewed-by: Pavel Machek
> 
> Include Pavel's email address.

Noted will fix in v6

> 
> > Cc: Wolfgang Denk <wd@denx.de>
> > CC: Pavel Machek <pavel@denx.de>
> > Cc: Dinh Nguyen <dinguyen@altera.com>
> > Cc: Tom Rini <trini@ti.com>
> > Cc: Albert Aribaud <albert.u.boot@aribaud.net>
> > ---
> > Changes for v2:
> >    - Fixed the word wrap issue within patch
> > Changes for v3:
> >    - Fixed the long subject of the patch
> > Changes for v4:
> >    - Added change log for each revision change
> > Changes for v5:
> >    - Added Reviewed-by: Pavel Machek
> >    - Cc: Tom Rini
> 
> Re-org this to have the latest, v5 at the top.

Noted will fix in v6

Thanks 

Chin Liang

Patch

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index b5a7a9a..06aeba6 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -11,6 +11,8 @@ 
 /*
  * High level configuration
  */
+/* Virtual target or real hardware */
+#define CONFIG_SOCFPGA_VIRTUAL_TARGET
 
 #define CONFIG_ARMV7
 #define CONFIG_L2_OFF
@@ -21,11 +23,12 @@ 
 #define CONFIG_SINGLE_BOOTLOADER
 #define CONFIG_SOCFPGA
 
+/* base address for .text section */
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_TEXT_BASE		0x08000040
-#define V_NS16550_CLK			1000000
-#define CONFIG_BAUDRATE			57600
-#define CONFIG_SYS_HZ			1000
-#define CONFIG_TIMER_CLOCK_KHZ		2400
+#else
+#define CONFIG_SYS_TEXT_BASE		0x01000040
+#endif
 #define CONFIG_SYS_LOAD_ADDR		0x7fc0
 
 /* Console I/O Buffer Size */
@@ -154,7 +157,7 @@ 
 /* SDRAM Bank #1 */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 /* SDRAM memory size */
-#define PHYS_SDRAM_1_SIZE		0x80000000
+#define PHYS_SDRAM_1_SIZE		0x40000000
 
 #define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_MEMTEST_START	0x00000000
@@ -170,8 +173,13 @@ 
 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
 #define CONFIG_CONS_INDEX               1
 #define CONFIG_SYS_NS16550_COM1		UART0_BASE
-
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define V_NS16550_CLK			1000000
+#else
+#define V_NS16550_CLK			100000000
+#endif
+#define CONFIG_BAUDRATE			115200
 
 /*
  * FLASH
@@ -184,9 +192,15 @@ 
 /* This timer use eosc1 where the clock frequency is fixed
  * throughout any condition */
 #define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
-
 /* reload value when timer count to zero */
 #define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Timer info */
+#define CONFIG_SYS_HZ			1000
+#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
+#define CONFIG_TIMER_CLOCK_KHZ		2400
+#else
+#define CONFIG_TIMER_CLOCK_KHZ		25000
+#endif
 
 #define CONFIG_ENV_IS_NOWHERE