From patchwork Tue Aug 6 09:55:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: pekon gupta X-Patchwork-Id: 264965 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D1EE62C0079 for ; Tue, 6 Aug 2013 19:56:54 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 998E84A057; Tue, 6 Aug 2013 11:56:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RS6zPXRkyJWb; Tue, 6 Aug 2013 11:56:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C9E6C4A058; Tue, 6 Aug 2013 11:56:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EA1214A02D for ; Tue, 6 Aug 2013 11:56:00 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 8L7Q6eyUaLE7 for ; Tue, 6 Aug 2013 11:55:54 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 573E44A019 for ; Tue, 6 Aug 2013 11:55:42 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id r769tcq2019678; Tue, 6 Aug 2013 04:55:38 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id r769tcna002891; Tue, 6 Aug 2013 04:55:38 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.2.342.3; Tue, 6 Aug 2013 04:55:38 -0500 Received: from psplinux064.india.ti.com (psplinux064.india.ti.com [172.24.162.112]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id r769tUTq001372; Tue, 6 Aug 2013 04:55:36 -0500 From: Pekon Gupta To: , Date: Tue, 6 Aug 2013 15:25:19 +0530 Message-ID: <1375782920-25935-4-git-send-email-pekon@ti.com> X-Mailer: git-send-email 1.8.1 In-Reply-To: <1375782920-25935-1-git-send-email-pekon@ti.com> References: <1375782920-25935-1-git-send-email-pekon@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v1 3/4] mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by processing the data passed during Read/Write accesses. All H/W based ECC schemes use GPMC controller to calculate ECC syndrome. But each BCHx_ECC scheme has its own implemetation of post-processing and fetching ECC syndrome from GPMC controller. This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way: - merges various sub-functions into single omap_calculate_ecc_bch(). - removes omap_ecc_disable() and instead uses it as inline. Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap_gpmc.c | 82 ++++++++++---------------------------------- 1 file changed, 18 insertions(+), 64 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index f3b86e5..40b71a7 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -281,34 +281,26 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) writel(ecc_config_val | 0x1, &gpmc_cfg->ecc_config); } -/* - * omap_ecc_disable - Disable H/W ECC calculation - * - * @mtd: MTD device structure - */ -static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) -{ - writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); -} #if defined(CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW) /* - * BCH8 support (needs ELM and thus AM33xx-only) - */ -/* - * omap_read_bch8_result - Read BCH result for BCH8 level + * omap_calculate_ecc_bch - Read BCH ECC result * - * @mtd: MTD device structure - * @big_endian: When set read register 3 first - * @ecc_code: Read syndrome from BCH result registers + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer */ -static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + int8_t ret = 0; uint32_t *ptr; int8_t i = 0, j; - if (big_endian) { + switch (bch->type) { + case ECC_BCH8: ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; ecc_code[i++] = readl(ptr) & 0xFF; ptr--; @@ -319,18 +311,13 @@ static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, ecc_code[i++] = readl(ptr) & 0xFF; ptr--; } - } else { - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0]; - for (j = 0; j < 3; j++) { - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ptr++; - } - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = 0; /* 14th byte is always zero */ + break; + default: + ret = -1; } + /* clear result and disable engine */ + writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); + return ret; } /* @@ -369,35 +356,6 @@ static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, } /* - * omap_calculate_ecc_bch - Read BCH ECC result - * - * @mtd: MTD structure - * @dat: unused - * @ecc_code: ecc_code buffer - */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) -{ - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t big_endian = 1; - int8_t ret = 0; - - if (bch->type == ECC_BCH8) - omap_read_bch8_result(mtd, big_endian, ecc_code); - else /* BCH4 and BCH16 currently not supported */ - ret = -1; - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); - - return ret; -} - -/* * omap_fix_errors_bch - Correct bch error in the data * * @mtd: MTD device structure @@ -594,12 +552,8 @@ static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); *ecc++ = 0xb5 ^ (val1 & 0xFF); } - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); + /* Stop reading anymore ECC vals and clear old results */ + writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); return ret; }