From patchwork Tue Aug 6 00:53:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Chubb X-Patchwork-Id: 264826 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B67562C0079 for ; Tue, 6 Aug 2013 10:54:01 +1000 (EST) Received: from localhost ([::1]:57429 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6VXC-0006ZY-SF for incoming@patchwork.ozlabs.org; Mon, 05 Aug 2013 20:53:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6VWo-0006ZG-OQ for qemu-devel@nongnu.org; Mon, 05 Aug 2013 20:53:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6VWi-0008IQ-1r for qemu-devel@nongnu.org; Mon, 05 Aug 2013 20:53:34 -0400 Received: from lemon.ertos.nicta.com.au ([203.143.174.143]:58505) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6VWh-0008Hz-Fv for qemu-devel@nongnu.org; Mon, 05 Aug 2013 20:53:27 -0400 Received: from [2402:1800:4000:2:224:d7ff:feaf:390] (port=53444 helo=Diprotodon.chubb.wattle.id.au) by lemon.ertos.nicta.com.au with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA1:128) (Exim 4.80) (envelope-from ) id 1V6VVm-00040g-Pd; Tue, 06 Aug 2013 10:52:33 +1000 Date: Tue, 06 Aug 2013 10:53:11 +1000 Message-ID: <84wqnzk5c8.wl%peter.chubb@nicta.com.au> From: Peter Chubb To: Andreas =?ISO-8859-1?Q?F=E4rber?= In-Reply-To: <51FF6F67.8070101@suse.de> References: <84r4e9j5ko.wl%peter.chubb@nicta.com.au> <51FF6F67.8070101@suse.de> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL/10.8 EasyPG/1.0.0 Emacs/23.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) X-Face: GgFg(Z>fx((4\32hvXq<)|jndSniCH~~$D)Ka:P@e@JR1P%Vr}EwUdfwf-4j\rUs#JR{'h# !]])6%Jh~b$VA|ALhnpPiHu[-x~@<"@Iv&|%R)Fq[[, (&Z'O)Q)xCqe1\M[F8#9l8~}#u$S$Rm`S9% \'T@`:&8>Sb*c5d'=eDYI&GF`+t[LfDH="MP5rwOO]w>ALi7'=QJHz&y&C&TE_3j! Organization: NICTA MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 2402:1800:4000:2:224:d7ff:feaf:390 X-SA-Exim-Mail-From: peter.chubb@nicta.com.au X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:56:45 +0000) X-SA-Exim-Scanned: Yes (on lemon.ertos.nicta.com.au) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 203.143.174.143 Cc: Peter Maydell , Peter Chubb , qemu-devel@nongnu.org, Jan Kiszka Subject: Re: [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org >>>>> "Andreas" == Andreas Färber writes: Andreas> Peter Ch., if you know the exact differences, why don't you Andreas> just derive an imx-l2cc type (or so) derived from ARM's type, Andreas> overriding the values mentioned above? Sounds trivial to me. For what it's worth, here's a diff between the arm_l2x0.c implementation and a working imx_l2cc.c implementation. Most of the diffs are name change; but there are substantive differences to the initial values, and to which registers are supported. This makes the State variable smaller. So it's a bit more than just overriding a few constants. --- Dr Peter Chubb peter.chubb AT nicta.com.au http://www.ssrg.nicta.com.au Software Systems Research Group/NICTA --- arm_l2x0.c 2013-08-06 09:59:30.008468028 +1000 +++ imx-l2cc-indep.c 2013-08-06 10:49:38.021514073 +1000 @@ -1,7 +1,10 @@ /* - * ARM dummy L210, L220, PL310 cache controller. + * IMX dummy level 2 cache controller * - * Copyright (c) 2010-2012 Calxeda + * Copyright (c) 2013 NICTA Peter Chubb + * + * Based on the PL210 implementation in arm_l2x0.c + * Differences: different Cache ID and aux control register values. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,46 +23,40 @@ #include "hw/sysbus.h" -/* L2C-310 r3p2 */ -#define CACHE_ID 0x410000c8 -#define TYPE_ARM_L2X0 "l2x0" -#define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0) +#define CACHE_ID 0xd5000041 +#define CACHE_TYPE_DEFAULT 0x1C100100 + +#define TYPE_IMX_L2CC "imx_l2cc" +#define IMX_L2CC(obj) OBJECT_CHECK(L2ccState, (obj), TYPE_IMX_L2CC) -typedef struct L2x0State { +typedef struct L2ccState { SysBusDevice parent_obj; MemoryRegion iomem; uint32_t cache_type; uint32_t ctrl; uint32_t aux_ctrl; - uint32_t data_ctrl; - uint32_t tag_ctrl; - uint32_t filter_start; - uint32_t filter_end; -} L2x0State; +} L2ccState; -static const VMStateDescription vmstate_l2x0 = { - .name = "l2x0", +static const VMStateDescription vmstate_l2cc = { + .name = "imx_l2cc", .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32(ctrl, L2x0State), - VMSTATE_UINT32(aux_ctrl, L2x0State), - VMSTATE_UINT32(data_ctrl, L2x0State), - VMSTATE_UINT32(tag_ctrl, L2x0State), - VMSTATE_UINT32(filter_start, L2x0State), - VMSTATE_UINT32(filter_end, L2x0State), + VMSTATE_UINT32(ctrl, L2ccState), + VMSTATE_UINT32(cache_type, L2ccState), + VMSTATE_UINT32(aux_ctrl, L2ccState), VMSTATE_END_OF_LIST() } }; -static uint64_t l2x0_priv_read(void *opaque, hwaddr offset, +static uint64_t l2cc_priv_read(void *opaque, hwaddr offset, unsigned size) { uint32_t cache_data; - L2x0State *s = (L2x0State *)opaque; + L2ccState *s = (L2ccState *)opaque; offset &= 0xfff; if (offset >= 0x730 && offset < 0x800) { return 0; /* cache ops complete */ @@ -76,32 +73,20 @@ return s->ctrl; case 0x104: return s->aux_ctrl; - case 0x108: - return s->tag_ctrl; - case 0x10C: - return s->data_ctrl; - case 0xC00: - return s->filter_start; - case 0xC04: - return s->filter_end; case 0xF40: return 0; - case 0xF60: - return 0; - case 0xF80: - return 0; default: qemu_log_mask(LOG_GUEST_ERROR, - "l2x0_priv_read: Bad offset %x\n", (int)offset); + "l2cc_priv_read: Bad offset %x\n", (int)offset); break; } return 0; } -static void l2x0_priv_write(void *opaque, hwaddr offset, +static void l2cc_priv_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - L2x0State *s = (L2x0State *)opaque; + L2ccState *s = (L2ccState *)opaque; offset &= 0xfff; if (offset >= 0x730 && offset < 0x800) { /* ignore */ @@ -114,86 +99,61 @@ case 0x104: s->aux_ctrl = value; break; - case 0x108: - s->tag_ctrl = value; - break; - case 0x10C: - s->data_ctrl = value; - break; - case 0xC00: - s->filter_start = value; - break; - case 0xC04: - s->filter_end = value; - break; case 0xF40: return; - case 0xF60: - return; - case 0xF80: - return; default: qemu_log_mask(LOG_GUEST_ERROR, - "l2x0_priv_write: Bad offset %x\n", (int)offset); + "l2cc_priv_write: Bad offset %x\n", (int)offset); break; } } -static void l2x0_priv_reset(DeviceState *dev) +static void l2cc_priv_reset(DeviceState *dev) { - L2x0State *s = ARM_L2X0(dev); + L2ccState *s = IMX_L2CC(dev); s->ctrl = 0; - s->aux_ctrl = 0x02020000; - s->tag_ctrl = 0; - s->data_ctrl = 0; - s->filter_start = 0; - s->filter_end = 0; + s->cache_type = CACHE_TYPE_DEFAULT; + s->aux_ctrl = 0xE4020FFF; } -static const MemoryRegionOps l2x0_mem_ops = { - .read = l2x0_priv_read, - .write = l2x0_priv_write, +static const MemoryRegionOps l2cc_mem_ops = { + .read = l2cc_priv_read, + .write = l2cc_priv_write, .endianness = DEVICE_NATIVE_ENDIAN, }; -static int l2x0_priv_init(SysBusDevice *dev) +static int l2cc_priv_init(SysBusDevice *dev) { - L2x0State *s = ARM_L2X0(dev); + L2ccState *s = IMX_L2CC(dev); - memory_region_init_io(&s->iomem, OBJECT(dev), &l2x0_mem_ops, s, - "l2x0_cc", 0x1000); + memory_region_init_io(&s->iomem, OBJECT(dev), &l2cc_mem_ops, s, + "l2cc_cc", 0x1000); sysbus_init_mmio(dev, &s->iomem); return 0; } -static Property l2x0_properties[] = { - DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100), - DEFINE_PROP_END_OF_LIST(), -}; - -static void l2x0_class_init(ObjectClass *klass, void *data) +static void l2cc_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - k->init = l2x0_priv_init; - dc->vmsd = &vmstate_l2x0; + k->init = l2cc_priv_init; + dc->vmsd = &vmstate_l2cc; dc->no_user = 1; - dc->props = l2x0_properties; - dc->reset = l2x0_priv_reset; + dc->reset = l2cc_priv_reset; } -static const TypeInfo l2x0_info = { - .name = TYPE_ARM_L2X0, +static const TypeInfo l2cc_info = { + .name = TYPE_IMX_L2CC, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(L2x0State), - .class_init = l2x0_class_init, + .instance_size = sizeof(L2ccState), + .class_init = l2cc_class_init, }; -static void l2x0_register_types(void) +static void l2cc_register_types(void) { - type_register_static(&l2x0_info); + type_register_static(&l2cc_info); } -type_init(l2x0_register_types) +type_init(l2cc_register_types)