Patchwork [U-Boot,1/7] arm, am335x: add some missing registers and defines for lcd and epwm support

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Submitter Heiko Schocher
Date Aug. 3, 2013, 5:22 a.m.
Message ID <1375507373-13785-2-git-send-email-hs@denx.de>
Download mbox | patch
Permalink /patch/264386/
State Superseded
Delegated to: Tom Rini
Headers show

Comments

Heiko Schocher - Aug. 3, 2013, 5:22 a.m.
- add missing register defines in struct cm_perpl
  epwmss0clkctrl
  epwmss2clkctrl
  lcdcclkstctrl
- add missing register defines in struct cm_dpll
  clklcdcpixelclk
- add struct pwmss_regs
- add struct pwmss_ecap_regs
- add LCD Controller base LCD_CNTL_BASE
- add PWM0 controller base PWMSS0_BASE

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>
---
 arch/arm/include/asm/arch-am33xx/cpu.h             | 35 +++++++++++++++++++++-
 arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |  7 +++++
 2 Dateien geändert, 41 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)
Tom Rini - Aug. 6, 2013, 3:22 p.m.
On Sat, Aug 03, 2013 at 07:22:47AM +0200, Heiko Schocher wrote:

[snip]
> +struct pwmss_ecap_regs {
> +	unsigned int tsctr;
> +	unsigned int ctrphs;
> +	unsigned int cap1;
> +	unsigned int cap2;
> +	unsigned int cap3;
> +	unsigned int cap4;
> +	unsigned int reserved[4];

We use 'resv' in the rest of the am33xx headers, please do 'resv1[4]'
instead for consistency.

> diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> index 432f0c7..293ede2 100644
> --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
> @@ -43,4 +43,11 @@
>  /* RTC base address */
>  #define RTC_BASE			0x44E3E000
>  
> +/* LCD Controller */
> +#define	LCD_CNTL_BASE			0x4830E000

#define<space> not <tab>. Thanks.

Patch

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index ce24080..daaf13c 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -219,7 +219,8 @@  struct cm_perpll {
 	unsigned int dcan1clkctrl;	/* offset 0xC4 */
 	unsigned int resv6[2];
 	unsigned int emiffwclkctrl;	/* offset 0xD0 */
-	unsigned int resv7[2];
+	unsigned int epwmss0clkctrl;	/* offset 0xD4 */
+	unsigned int epwmss2clkctrl;	/* offset 0xD8 */
 	unsigned int l3instrclkctrl;	/* offset 0xDC */
 	unsigned int l3clkctrl;		/* Offset 0xE0 */
 	unsigned int resv8[4];
@@ -230,12 +231,15 @@  struct cm_perpll {
 	unsigned int l4hsclkctrl;	/* offset 0x120 */
 	unsigned int resv10[8];
 	unsigned int cpswclkstctrl;	/* offset 0x144 */
+	unsigned int lcdcclkstctrl;	/* offset 0x148 */
 };
 
 /* Encapsulating Display pll registers */
 struct cm_dpll {
 	unsigned int resv1[2];
 	unsigned int clktimer2clk;	/* offset 0x08 */
+	unsigned int resv2[10];
+	unsigned int clklcdcpixelclk;	/* offset 0x34 */
 };
 
 /* Control Module RTC registers */
@@ -377,6 +381,35 @@  struct ctrl_dev {
 #define RGMII_INT_DELAY		(RGMII1_IDMODE | RGMII2_IDMODE)
 #define RMII_CHIPCKL_ENABLE     (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
 
+/* PWMSS */
+struct pwmss_regs {
+	unsigned int idver;
+	unsigned int sysconfig;
+	unsigned int clkconfig;
+	unsigned int clkstatus;
+};
+#define ECAP_CLK_EN		BIT(0)
+#define ECAP_CLK_STOP_REQ	BIT(1)
+
+struct pwmss_ecap_regs {
+	unsigned int tsctr;
+	unsigned int ctrphs;
+	unsigned int cap1;
+	unsigned int cap2;
+	unsigned int cap3;
+	unsigned int cap4;
+	unsigned int reserved[4];
+	unsigned short ecctl1;
+	unsigned short ecctl2;
+};
+
+/* Capture Control register 2 */
+#define ECTRL2_SYNCOSEL_MASK	(0x03 << 6)
+#define ECTRL2_MDSL_ECAP	BIT(9)
+#define ECTRL2_CTRSTP_FREERUN	BIT(4)
+#define ECTRL2_PLSL_LOW		BIT(10)
+#define ECTRL2_SYNC_EN		BIT(5)
+
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL_STRICT_NAMES */
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
index 432f0c7..293ede2 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
@@ -43,4 +43,11 @@ 
 /* RTC base address */
 #define RTC_BASE			0x44E3E000
 
+/* LCD Controller */
+#define	LCD_CNTL_BASE			0x4830E000
+
+/* PWMSS */
+#define PWMSS0_BASE			0x48300000
+#define AM33XX_ECAP0_BASE		0x48300100
+
 #endif /* __AM33XX_HARDWARE_AM33XX_H */