===================================================================
@@ -33822,7 +33822,7 @@
if (TARGET_64BIT
&& MEM_P (x)
&& GET_MODE_SIZE (mode) > UNITS_PER_WORD
- && rclass == GENERAL_REGS
+ && INTEGER_CLASS_P (rclass)
&& !offsettable_memref_p (x))
{
sri->icode = (in_p
@@ -33838,12 +33838,8 @@
intermediate register on 32bit targets. */
if (!TARGET_64BIT
&& !in_p && mode == QImode
- && (rclass == GENERAL_REGS
- || rclass == LEGACY_REGS
- || rclass == NON_Q_REGS
- || rclass == SIREG
- || rclass == DIREG
- || rclass == INDEX_REGS))
+ && INTEGER_CLASS_P (rclass)
+ && MAYBE_NON_Q_CLASS_P (rclass))
{
int regno;
===================================================================
@@ -1288,13 +1288,16 @@
#define MAYBE_FLOAT_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), FLOAT_REGS)
#define MAYBE_SSE_CLASS_P(CLASS) \
- reg_classes_intersect_p (SSE_REGS, (CLASS))
+ reg_classes_intersect_p ((CLASS), SSE_REGS)
#define MAYBE_MMX_CLASS_P(CLASS) \
- reg_classes_intersect_p (MMX_REGS, (CLASS))
+ reg_classes_intersect_p ((CLASS), MMX_REGS)
#define Q_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), Q_REGS)
+#define MAYBE_NON_Q_CLASS_P(CLASS) \
+ reg_classes_intersect_p ((CLASS), NON_Q_REGS)
+
/* Give names of register classes as strings for dump file. */
#define REG_CLASS_NAMES \