Patchwork net/phy: micrel: Add OF configuration support

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Submitter Sean Cross
Date Aug. 1, 2013, 4:16 a.m.
Message ID <1375330601-3609-2-git-send-email-xobs@kosagi.com>
Download mbox | patch
Permalink /patch/263897/
State Changes Requested
Delegated to: David Miller
Headers show

Comments

Sean Cross - Aug. 1, 2013, 4:16 a.m.
Some boards require custom PHY configuration, for example due to trace
length differences.  Add the ability to configure these registers in
order to get the PHY to function on boards that need it.

Because PHYs are auto-detected based on MDIO device IDs, allow PHY
configuration to be specified in the parent Ethernet device node if no
PHY device node is present.

Signed-off-by: Sean Cross <xobs@kosagi.com>
---
 .../devicetree/bindings/net/micrel-phy.txt         |   20 +++++++
 drivers/net/phy/micrel.c                           |   57 ++++++++++++++++++++
 2 files changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/micrel-phy.txt
Nimrod Andy - Aug. 1, 2013, 5:31 a.m.
On Thu, Aug 01, 2013 at 12:17 PM, Sean Cross wrote:

> +/* Write/read to/from extended registers */
> +#define MII_KSZPHY_EXTREG                       0x0b
> +#define KSZPHY_EXTREG_WRITE                     0x8000
> +
> +#define MII_KSZPHY_EXTREG_WRITE                 0x0c
> +#define MII_KSZPHY_EXTREG_READ                  0x0d
> +
> +/* Write/read to/from extended registers */
> +#define MII_KSZPHY_EXTREG                       0x0b
> +#define KSZPHY_EXTREG_WRITE                     0x8000
> +
> +#define MII_KSZPHY_EXTREG_WRITE                 0x0c
> +#define MII_KSZPHY_EXTREG_READ                  0x0d
> +

Pls don't re-define the registers address and field.

> +		if (!of_property_read_u32(of_node,
> +					  "micrel,clk-control-pad-skew",
> +					  &val))
> +			kszphy_extended_write(phydev,
> +					      MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
> +					      val);

When re-set rx/tx clock delay, rx/tx control delay, it is better to do dummy read the extended MII_KSZPHY_CLK_CONTROL_PAD_SKEW register one time.

Thanks,
Andy


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Sean Cross - Aug. 1, 2013, 6:23 a.m.
On Thursday, August 1, 2013 at 1:31 PM, Duan Fugang-B38611 wrote:
> On Thu, Aug 01, 2013 at 12:17 PM, Sean Cross wrote:
> 
> > +/* Write/read to/from extended registers */
> > +#define MII_KSZPHY_EXTREG 0x0b
> > +#define KSZPHY_EXTREG_WRITE 0x8000
> > +
> > +#define MII_KSZPHY_EXTREG_WRITE 0x0c
> > +#define MII_KSZPHY_EXTREG_READ 0x0d
> > +
> > +/* Write/read to/from extended registers */
> > +#define MII_KSZPHY_EXTREG 0x0b
> > +#define KSZPHY_EXTREG_WRITE 0x8000
> > +
> > +#define MII_KSZPHY_EXTREG_WRITE 0x0c
> > +#define MII_KSZPHY_EXTREG_READ 0x0d
> > +
> 
> 
> 
> Pls don't re-define the registers address and field.
My fault.  I'll remove this redundancy. 
> > + if (!of_property_read_u32(of_node,
> > + "micrel,clk-control-pad-skew",
> > + &val))
> > + kszphy_extended_write(phydev,
> > + MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
> > + val);
> 
> 
> 
> When re-set rx/tx clock delay, rx/tx control delay, it is better to do dummy read the extended MII_KSZPHY_CLK_CONTROL_PAD_SKEW register one time.
Can you please explain this?  I don't see anything in the datasheet I'm looking at (ksz9021rl) describing dummy reads.  If both tx and rx skew are adjusted, should there be two dummy reads or just one? 


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Nimrod Andy - Aug. 1, 2013, 6:52 a.m.
On Thursday, August 1, 2013 at 2:23 PM, Sean Cross wrote:
>> When re-set rx/tx clock delay, rx/tx control delay, it is better to do dummy read the extended MII_KSZPHY_CLK_CONTROL_PAD_SKEW register one time.

> Can you please explain this?  I don't see anything in the datasheet I'm looking at (ksz9021rl) describing dummy reads.

> If both tx and rx skew are adjusted, should there be >two dummy reads or just one? 


When freescale engineers do the phy bring up, they add the dummy read. Pls refer the the patchwork: http://patchwork.ozlabs.org/patch/246616/
From ksz9021r1, there have no such condition. After I remove the dummy read, the imx6q sabrelite platform ethernet Gbps mode work fine.
For at91 micrel phy fixup, there have no dummy read: http://lists.infradead.org/pipermail/linux-arm-kernel/2013-July/183626.html
So, it just one confuse, and the dummy read is unnecessary.

Patch

diff --git a/Documentation/devicetree/bindings/net/micrel-phy.txt b/Documentation/devicetree/bindings/net/micrel-phy.txt
new file mode 100644
index 0000000..97c1ef2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/micrel-phy.txt
@@ -0,0 +1,20 @@ 
+Micrel KS8737, KSZ8041, KSZ8001, KS8721, KSZ8081, KSZ8091, KSZ8061, KSZ9021,
+KSZ9031, Ethernet PHYs, and KSZ8873MLL and KSZ886X Ethernet switches.
+
+Some boards require special tuning values, particularly when it comes to
+clock delays.  You can specify clock delay values by adding
+micrel-specific properties to an Ethernet OF device node.
+
+Optional properties:
+- micrel,clk-control-pad-skew : Timing offset for the MII clock line
+- micrel,rx-data-pad-skew : Timing offset for the RX MII pad
+- micrel,tx-data-pad-skew : Timing offset for the TX MII pad
+
+Example:
+	&enet {
+		micrel,clk-control-pad-skew = <0xf0f0>;
+		micrel,rx-data-pad-skew = <0x0000>;
+		micrel,tx-data-pad-skew = <0xffff>;
+		status = "okay";
+	};
+
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 2510435..0abe821 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -25,6 +25,7 @@ 
 #include <linux/module.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <linux/of.h>
 
 /* Operation Mode Strap Override */
 #define MII_KSZPHY_OMSO				0x16
@@ -53,6 +54,25 @@ 
 #define KS8737_CTRL_INT_ACTIVE_HIGH		(1 << 14)
 #define KSZ8051_RMII_50MHZ_CLK			(1 << 7)
 
+/* Write/read to/from extended registers */
+#define MII_KSZPHY_EXTREG                       0x0b
+#define KSZPHY_EXTREG_WRITE                     0x8000
+
+#define MII_KSZPHY_EXTREG_WRITE                 0x0c
+#define MII_KSZPHY_EXTREG_READ                  0x0d
+
+/* Write/read to/from extended registers */
+#define MII_KSZPHY_EXTREG                       0x0b
+#define KSZPHY_EXTREG_WRITE                     0x8000
+
+#define MII_KSZPHY_EXTREG_WRITE                 0x0c
+#define MII_KSZPHY_EXTREG_READ                  0x0d
+
+/* Extended registers */
+#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
+#define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
+#define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
+
 static int ksz_config_flags(struct phy_device *phydev)
 {
 	int regval;
@@ -65,6 +85,13 @@  static int ksz_config_flags(struct phy_device *phydev)
 	return 0;
 }
 
+static int kszphy_extended_write(struct phy_device *phydev,
+                                 u32 regnum, u16 val)
+{
+	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
+	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
+}
+
 static int kszphy_ack_interrupt(struct phy_device *phydev)
 {
 	/* bit[7..0] int status, which is a read and clear register. */
@@ -121,6 +148,36 @@  static int ks8737_config_intr(struct phy_device *phydev)
 
 static int kszphy_config_init(struct phy_device *phydev)
 {
+	struct device *dev = &phydev->dev;
+	struct device_node *of_node = dev->of_node;
+
+	if (!of_node && dev->parent->of_node)
+		of_node = dev->parent->of_node;
+
+	if (of_node) {
+		u32 val;
+
+		if (!of_property_read_u32(of_node,
+					  "micrel,clk-control-pad-skew",
+					  &val))
+			kszphy_extended_write(phydev,
+					      MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
+					      val);
+
+		if (!of_property_read_u32(of_node,
+					  "micrel,rx-data-pad-skew",
+					  &val))
+			kszphy_extended_write(phydev,
+					      MII_KSZPHY_RX_DATA_PAD_SKEW,
+					      val);
+
+		if (!of_property_read_u32(of_node,
+					  "micrel,tx-data-pad-skew",
+					  &val))
+			kszphy_extended_write(phydev,
+					      MII_KSZPHY_TX_DATA_PAD_SKEW,
+					      val);
+	}
 	return 0;
 }