| Message ID | 1375239547-8259-1-git-send-email-Minghuan.Lian@freescale.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | 0e3d4373b8a7757a8f5187f5cabafb6aceff469b |
| Delegated to: | Scott Wood |
| Headers | show |
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi index e5cf6c8..9813975 100644 --- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi +++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi @@ -41,7 +41,7 @@ &rio { compatible = "fsl,srio"; - interrupts = <16 2 1 11>; + interrupts = <16 2 1 20>; #address-cells = <2>; #size-cells = <2>; fsl,iommu-parent = <&pamu0>;
For B4 platform, MPIC EISR register is in reversed bitmap order, instead of "Error interrupt source 0-31. Bit 0 represents SRC0." the correct ordering is "Error interrupt source 0-31. Bit 0 represents SRC31." This patch is to fix sRIO EISR bit value of error interrupt in dts node. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> --- arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)