Patchwork powerpc/dts: fix sRIO error interrupt for b4860

login
register
mail settings
Submitter Minghuan Lian
Date July 31, 2013, 2:59 a.m.
Message ID <1375239547-8259-1-git-send-email-Minghuan.Lian@freescale.com>
Download mbox | patch
Permalink /patch/263563/
State Accepted, archived
Commit 0e3d4373b8a7757a8f5187f5cabafb6aceff469b
Delegated to: Scott Wood
Headers show

Comments

Minghuan Lian - July 31, 2013, 2:59 a.m.
For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
---
 arch/powerpc/boot/dts/fsl/b4860si-post.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index e5cf6c8..9813975 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -41,7 +41,7 @@ 
 
 &rio {
 	compatible = "fsl,srio";
-	interrupts = <16 2 1 11>;
+	interrupts = <16 2 1 20>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 	fsl,iommu-parent = <&pamu0>;