Patchwork [U-Boot,v7,11/11] arm: add Faraday A360/A369 SoC platform support

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Submitter Kuo-Jung Su
Date July 29, 2013, 5:51 a.m.
Message ID <1375077113-27251-12-git-send-email-dantesu@gmail.com>
Download mbox | patch
Permalink /patch/262690/
State Changes Requested
Delegated to: Albert ARIBAUD
Headers show

Comments

Kuo-Jung Su - July 29, 2013, 5:51 a.m.
From: Kuo-Jung Su <dantesu@faraday-tech.com>

This adds board support for the Faraday A360/A369 SoC platforms.

Working functions:
- MMU/D-cache
- SD Host controller
- USB EHCI controller
- USB Gadget controller
- Network
- NAND

Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
---
Changes for v7:
   - Update license to use SPDX identifiers.

Changes for v6:
   - arch/arm/cpu/faraday/cpu.c:
     struct ftwdt010_wdt __iomem *regs -> struct ftwdt010_wdt *regs

Changes for v5:
   - Coding Style cleanup:
     1. struct chip_regs __iomem *regs -> struct chip_regs *regs
     2. Move Faraday specific APIs into asm/arch-faraday/*.h
   - Fix Copyright notices (dates) throughout the patch
   - Define Faraday machine type in board's config header file
   - Add myself as the maintainer for Faraday A360/A369 in MAINTAINERS.
   - Drop i2c:FTI2C010 & spi:FTSSP010_SPI support. The corresponding patch
     would restart after this patch series have been accepted.
   - Revise clock management system

Changes for v4:
   - Coding Style cleanup.
   - Break-down the interrupt, timers and common utilties.

Changes for v3:
   - Coding Style cleanup.
   - Drop macros for wirtel()/readl(), call them directly.
   - Always insert a blank line between declarations and code.
   - Add '__iomem' to all the declaration of HW register pointers.
   - a36x_config: No more static global network configurations.
   - a36x_config: Add a common file for the redundant configurations.

Changes for v2:
   - Coding Style cleanup.
   - Use readl(), writel(), clrsetbits_le32() to replace REG() macros.
   - Use structure based hardware registers to replace the macro constants.
   - Replace BIT() with BIT_MASK().

 MAINTAINERS                                   |    5 +
 arch/arm/cpu/faraday/a360/Makefile            |   33 ++++
 arch/arm/cpu/faraday/a369/Makefile            |   34 ++++
 arch/arm/cpu/faraday/a369/cmd_fa606.c         |   74 ++++++++
 arch/arm/include/asm/arch-a360/hardware.h     |   72 ++++++++
 arch/arm/include/asm/arch-a360/pmu.h          |   83 +++++++++
 arch/arm/include/asm/arch-a360/scu.h          |   67 +++++++
 arch/arm/include/asm/arch-a369/ahbc.h         |   22 +++
 arch/arm/include/asm/arch-a369/hardware.h     |   86 +++++++++
 arch/arm/include/asm/arch-a369/scu.h          |  212 ++++++++++++++++++++++
 arch/arm/include/asm/arch-faraday/clock.h     |   29 +++
 arch/arm/include/asm/arch-faraday/interrupt.h |   17 ++
 board/faraday/a360evb/Makefile                |   29 +++
 board/faraday/a360evb/board.c                 |   71 ++++++++
 board/faraday/a360evb/clock.c                 |   71 ++++++++
 board/faraday/a360evb/config.mk               |   17 ++
 board/faraday/a360evb/lowlevel_init.S         |   16 ++
 board/faraday/a369evb/Makefile                |   29 +++
 board/faraday/a369evb/board.c                 |  175 ++++++++++++++++++
 board/faraday/a369evb/clock.c                 |   81 +++++++++
 board/faraday/a369evb/config.mk               |   17 ++
 board/faraday/a369evb/lowlevel_init.S         |  119 ++++++++++++
 boards.cfg                                    |    3 +
 include/common.h                              |    2 +
 include/configs/a360.h                        |   70 +++++++
 include/configs/a369-common.h                 |   85 +++++++++
 include/configs/a369.h                        |   47 +++++
 include/configs/a369_fa606te.h                |   40 ++++
 include/configs/faraday-common.h              |  242 +++++++++++++++++++++++++
 include/faraday/ftsmc020.h                    |    1 +
 30 files changed, 1849 insertions(+)
 create mode 100644 arch/arm/cpu/faraday/a360/Makefile
 create mode 100644 arch/arm/cpu/faraday/a369/Makefile
 create mode 100644 arch/arm/cpu/faraday/a369/cmd_fa606.c
 create mode 100644 arch/arm/include/asm/arch-a360/hardware.h
 create mode 100644 arch/arm/include/asm/arch-a360/pmu.h
 create mode 100644 arch/arm/include/asm/arch-a360/scu.h
 create mode 100644 arch/arm/include/asm/arch-a369/ahbc.h
 create mode 100644 arch/arm/include/asm/arch-a369/hardware.h
 create mode 100644 arch/arm/include/asm/arch-a369/scu.h
 create mode 100644 arch/arm/include/asm/arch-faraday/clock.h
 create mode 100644 arch/arm/include/asm/arch-faraday/interrupt.h
 create mode 100644 board/faraday/a360evb/Makefile
 create mode 100644 board/faraday/a360evb/board.c
 create mode 100644 board/faraday/a360evb/clock.c
 create mode 100644 board/faraday/a360evb/config.mk
 create mode 100644 board/faraday/a360evb/lowlevel_init.S
 create mode 100644 board/faraday/a369evb/Makefile
 create mode 100644 board/faraday/a369evb/board.c
 create mode 100644 board/faraday/a369evb/clock.c
 create mode 100644 board/faraday/a369evb/config.mk
 create mode 100644 board/faraday/a369evb/lowlevel_init.S
 create mode 100644 include/configs/a360.h
 create mode 100644 include/configs/a369-common.h
 create mode 100644 include/configs/a369.h
 create mode 100644 include/configs/a369_fa606te.h
 create mode 100644 include/configs/faraday-common.h

--
1.7.9.5

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 081cf96..c0d4417 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -644,6 +644,11 @@  Po-Yu Chuang <ratbert@faraday-tech.com>

 	a320evb		FA526 (ARM920T-like) (a320 SoC)

+Kuo-Jung Su <dantesu@faraday-tech.com>
+
+	a360evb		FA626TE (Faraday ARMv5TE) (a360 SoC)
+	a369evb		FA626TE & FA606TE (Faraday ARMv5TE) (a369 SoC)
+
 Eric Cooper <ecc@cmu.edu>

 	dockstar	ARM926EJS (Kirkwood SoC)
diff --git a/arch/arm/cpu/faraday/a360/Makefile b/arch/arm/cpu/faraday/a360/Makefile
new file mode 100644
index 0000000..aecae59
--- /dev/null
+++ b/arch/arm/cpu/faraday/a360/Makefile
@@ -0,0 +1,33 @@ 
+#
+# (C) Copyright 2013 Faraday Technology
+# Dante Su <dantesu@faraday-tech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+obj-y   :=
+
+COBJS	:= $(obj-y)
+SOBJS	:=
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/faraday/a369/Makefile b/arch/arm/cpu/faraday/a369/Makefile
new file mode 100644
index 0000000..69376c3
--- /dev/null
+++ b/arch/arm/cpu/faraday/a369/Makefile
@@ -0,0 +1,34 @@ 
+#
+# (C) Copyright 2013 Faraday Technology
+# Dante Su <dantesu@faraday-tech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+obj-y   :=
+obj-$(CONFIG_CMD_FA606) += cmd_fa606.o
+
+COBJS	:= $(obj-y)
+SOBJS	:=
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/faraday/a369/cmd_fa606.c b/arch/arm/cpu/faraday/a369/cmd_fa606.c
new file mode 100644
index 0000000..e23dc3c
--- /dev/null
+++ b/arch/arm/cpu/faraday/a369/cmd_fa606.c
@@ -0,0 +1,74 @@ 
+/*
+ * arch/arm/cpu/faraday/a369/cmd_fa606.c
+ *
+ * This command would activate the slave cpu (FA606TE)
+ * and then immediately halt the master cpu (FA626TE).
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/ahbc.h>
+
+static struct a369scu_regs *scu = (void __iomem *)CONFIG_SCU_BASE;
+static struct a369ahbc_regs *ahbc = (void __iomem *)CONFIG_AHBC2_BASE;
+
+static int do_fa606(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned int addr = CONFIG_SYS_LOAD_ADDR;
+
+	if (argc >= 2)
+		addr = simple_strtoul(argv[1], NULL, 16);
+
+	printf("FA606TE Image@0x%08X\n", addr);
+	printf("FA626TE is going to halt...\n");
+
+	cleanup_before_linux();
+
+	/* 1. FA606TE address offset = 0 */
+	printf("FA606 address shift disable.\n");
+	writel(0x00000000, &ahbc->cpusao);
+
+	/* 2. Generate a long-jump to 0x00000000 */
+	writel(0xEA00000A, 0x00); /* b   0x30 */
+	writel(addr,       0x20);
+	writel(0xE3A00020, 0x30); /* mov r0, #32 ; 0x20 */
+	writel(0xE590F000, 0x34); /* ldr pc, [r0] */
+
+	/* 3. Pinmux = ICE + LCD */
+	writel(GPMUX_DEFAULT, &scu->gpmux);
+	writel(SCCFG0_DEFAULT, &scu->sccfg[0]);
+	writel(SCCFG1_DEFAULT, &scu->sccfg[1]);
+	writel(MFPMUX0_TS(1) | MFPMUX0_ISP(2) | MFPMUX0_SATA(1)
+		| MFPMUX0_EXTAHB(1), &scu->mfpmux[0]);
+	writel(MFPMUX1_SSP0(1), &scu->mfpmux[1]);
+	udelay(5000);
+
+	/* 4. FA606TE clock enable & reset */
+	writel(0x00000000, &scu->hclkgr);
+	udelay(5000);
+	writel(GPMUX_DEFAULT | GPMUX_CPUS_START, &scu->gpmux);
+
+	/* 5. FA626TE is going to halt... */
+	__asm__ __volatile__ (
+		"mov r0, #0\n"
+		"mcr p15,0,r0,c7,c0,4\n"
+		:
+		:
+		: "r0" /* clobber list */
+	);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	fa606, 2, 0, do_fa606,
+	"launch firmware with A369's built-in fa606te\n",
+	"fa606 [address] - mov pc of fa606te to the specified address.\n"
+);
diff --git a/arch/arm/include/asm/arch-a360/hardware.h b/arch/arm/include/asm/arch-a360/hardware.h
new file mode 100644
index 0000000..7037988
--- /dev/null
+++ b/arch/arm/include/asm/arch-a360/hardware.h
@@ -0,0 +1,72 @@ 
+/*
+ * arch/arm/include/asm/arch-a360/hardware.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#define CONFIG_SCU_BASE				0x99900000
+#define CONFIG_PMU_BASE				0x98100000
+#define CONFIG_PMU_IRQ				8
+
+/*
+ * Timer
+ */
+#define CONFIG_FTTMR010_BASE		0x98400000
+#define CONFIG_FTTMR010_IRQ			19
+
+/*
+ * UART
+ */
+#define CONFIG_FTUART010_BASE		0x98200000
+
+/*
+ * Interrupt
+ */
+#define CONFIG_FTINTC020_BASE		0x98800000
+
+/*
+ * WatchDog
+ */
+#define CONFIG_FTWDT010_BASE		0x98500000
+
+/*
+ * NIC
+ */
+#define CONFIG_FTMAC110_BASE		0x90900000
+
+/*
+ * NAND
+ */
+#define CONFIG_FTNANDC020_BASE		0x91000000
+
+/*
+ * I2C
+ */
+#define CONFIG_FTI2C010_BASE		0x98A00000
+
+/*
+ * SPI
+ */
+#define CONFIG_FTSSP010_BASE		0x98B00000
+#define CONFIG_FTSSP010_GPIO_BASE	0x98700000
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_FTSDC010_BASE        0x90700000
+
+/*
+ * USB
+ */
+#define CONFIG_FUSBH200_BASE        0x90A00000
+#define CONFIG_FOTG210_BASE         0x90B00000
+
+#endif
diff --git a/arch/arm/include/asm/arch-a360/pmu.h b/arch/arm/include/asm/arch-a360/pmu.h
new file mode 100644
index 0000000..300e1ea
--- /dev/null
+++ b/arch/arm/include/asm/arch-a360/pmu.h
@@ -0,0 +1,83 @@ 
+/*
+ * arch/arm/include/asm/arch-a360/pmu.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H
+
+struct a360pmu_regs {
+	uint32_t idr;      /* ID register */
+	uint32_t rsvd0;
+	uint32_t osccr;    /* OSC control register */
+	uint32_t pmr;      /* Power mode register */
+
+	uint32_t pmcr;     /* Power manager control register */
+	uint32_t peer;     /* Power manager edge detection enable register */
+	uint32_t pesr;     /* Power manager edge detection status register */
+	uint32_t rsvd1;
+
+	uint32_t pmsr;     /* Power manager status register */
+	uint32_t pgsr;     /* Power manager GPIO sleep state register */
+	uint32_t rsvd2;
+	uint32_t mcr;      /* Misc. control register */
+
+	uint32_t pdcr;     /* PLL/DLL control register */
+	uint32_t rsvd3[7];
+
+	uint32_t pspr[16]; /* Power manager scratch pad register */
+
+	uint32_t rsvd4[3];
+	uint32_t jssr;     /* Jumper setting status register */
+};
+
+#define OSCCR_STABLE    (1 << 9) /* OSCH is stable */
+#define OSCCR_DISABLE   (1 << 8) /* Disable OSCH */
+
+#define PMR_FCS         (1 << 2) /* Activate freq. change sequence */
+#define PMR_TURBO       (1 << 1) /* Activate CPU turbo mode (2 x AHB) */
+#define PMR_SLEEP       (1 << 0) /* Activate system sleep */
+
+#define PMCR_PWLOW      (1 << 5) /* Mask X_powerlow_b pin source */
+#define PMCR_WAIT       (1 << 4) /* Enable countdown for CPU power-off */
+#define PMCR_WDT        (1 << 3) /* Use WatchDog reset */
+#define PMCR_RTC        (1 << 2) /* Enable system wake-up from RTC alarm */
+#define PMCR_GPIO1      (1 << 1) /* Enable system wake-up from GPIO1 */
+#define PMCR_GPIO0      (1 << 0) /* Enable system wake-up from GPIO0 */
+
+#define PEER_GPIO1_RE   (1 << 9) /* Wake-up upon Rising-Edge of GPIO1 */
+#define PEER_GPIO0_RE   (1 << 8) /* Wake-up upon Rising-Edge of GPIO0 */
+#define PEER_GPIO1_FE   (1 << 1) /* Wake-up upon Falling-Edge of GPIO1 */
+#define PEER_GPIO0_FE   (1 << 0) /* Wake-up upon Falling-Edge of GPIO0 */
+
+#define PESR_RTC        (1 << 2) /* Wake-up from RTC */
+#define PESR_GPIO1      (1 << 1) /* Wake-up from GPIO1 */
+#define PESR_GPIO0      (1 << 0) /* Wake-up from GPIO0 */
+
+#define PMSR_PWLOW      (1 << 19)/* X_powerlow_b is pulled low */
+#define PMSR_ISR_PWLOW  (1 << 18)/* Interrupt Status: X_powerlow_b */
+#define PMSR_ISR_FCS    (1 << 17)/* Interrupt Status: FCS */
+#define PMSR_ISR_TURBO  (1 << 16)/* Interrupt Status: TURBO */
+#define PMSR_WAKEUP     (1 << 10)/* Wake-up from sleep mode */
+#define PMSR_WDT        (1 << 9) /* Reset by WatchDog */
+#define PMSR_HW         (1 << 8) /* Reset by Hardware */
+#define PMSR_NOGPI      (1 << 2) /* Disable GPIO input mode */
+#define PMSR_GPIO_HELD  (1 << 1) /* GPIO are held in sleep mode */
+
+#define PDCR_WAITDLLS   (1 << 23)/* Wait until DLL stable */
+#define PDCR_DLLS       (1 << 22)/* DLL is stable */
+#define PDCR_DDLL       (1 << 21)/* Disable DLL */
+#define PDCR_PLL1MS(x)  (((x) >> 11) & 0xf)/* PLL1 MS */
+#define PDCR_PLL1NS(x)  (((x) >> 3) & 0x3f)/* PLL1 NS */
+#define PDCR_WAITPLL1S  (1 << 2) /* Wait until PLL1 stable */
+#define PDCR_PLL1S      (1 << 1) /* PLL1 is stable */
+#define PDCR_DPLL1      (1 << 0) /* Disable PLL1 */
+
+#define JSSR_PLL1NS(x)  (((x) >> 2) & 0x3f)/* PLL1 NS */
+#define JSSR_OSC        (1 << 0) /* PLL1/DLL are disabled */
+
+#endif
diff --git a/arch/arm/include/asm/arch-a360/scu.h b/arch/arm/include/asm/arch-a360/scu.h
new file mode 100644
index 0000000..37c23eb
--- /dev/null
+++ b/arch/arm/include/asm/arch-a360/scu.h
@@ -0,0 +1,67 @@ 
+/*
+ * arch/arm/include/asm/arch-a360/scu.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SCU_H
+#define __ASM_ARCH_SCU_H
+
+struct a360scu_regs {
+	uint32_t idr;      /* 0x00: ID Register */
+	uint32_t gcr;      /* 0x04: General Control Register */
+	uint32_t ccr;      /* 0x08: Clock Configuration Register */
+	uint32_t hcer;     /* 0x0C: AHB Clock Enable Register */
+	uint32_t pcer;     /* 0x10: APB Clock Enable Register */
+	uint32_t csr;      /* 0x14: Configuration Strap Register */
+	uint32_t iomcr[4]; /* IO Mux Control Register */
+	uint32_t iopcr[2]; /* IO Parameter Control Register */
+	uint32_t cescr;    /* CPU Edge Sync Control Register */
+	uint32_t expcr[3]; /* PCI-Express Control Register */
+};
+
+#define GCR_LVBC_IRQ3       (1 << 25) /* LVBC interrupt 3 propagation */
+#define GCR_LVBC_IRQ2       (1 << 24) /* LVBC interrupt 2 propagation */
+#define GCR_LVTX_RATE(x)    (((x) & 0x1f) << 16) /* LVTX clock rate */
+#define GCR_LVTX_CLK_OUT    (1 << 13) /* Enable LVTX clock out */
+#define GCR_USBH1_PLL_ALIVE (1 << 11) /* USB Host PLL alive */
+#define GCR_USBH0_PLL_ALIVE (1 << 10) /* USB Host PLL alive */
+#define GCR_USBH1_CLK_OUT   (1 << 9) /* Enable USB Host clock out */
+#define GCR_USBH0_CLK_OUT   (1 << 8) /* Enable USB Host clock out */
+#define GCR_DEBUG           (1 << 7) /* Enable debug mode */
+#define GCR_DEBUG_SW        (1 << 6) /* Enable software debug mode */
+#define GCR_IM              (1 << 5) /* Interrupt mask */
+#define GCR_RESET           (1 << 4) /* Software reset */
+
+#define CCR_LVDSTX_DSEL(x)  (((x) >> 21) & 0x1f) /* LVDS Tx Clock Select */
+#define CCR_LVDSRX_DSEL(x)  (((x) >> 16) & 0x1f) /* LVDS Rx Clock Select */
+#define CCR_SSP1_CKFQ(x)    (((x) >> 12) & 0xf) /* SSP1 Clock Freq. */
+#define CCR_SSP0_CKFQ(x)    (((x) >> 8) & 0xf) /* SSP0 Clock Freq. */
+#define CCR_SSP1_EXTCLK     (1 << 7) /* SSP1 use external clock */
+#define CCR_SSP1_PCLK       (0 << 7) /* SSP1 use APB clock */
+#define CCR_SSP0_EXTCLK     (1 << 6) /* SSP0 use external clock */
+#define CCR_SSP0_PCLK       (0 << 6) /* SSP0 use APB clock */
+#define CCR_LVDSTX_HCLK     (0 << 4) /* LVDS Tx clock select */
+#define CCR_LVDSTX_PCLK     (1 << 4)
+#define CCR_LVDSTX_EXTCLK   (2 << 4)
+#define CCR_SDC_HCLK        (2 << 2) /* SD/MMC clock select */
+#define CCR_SDC_MCLK        (1 << 2)
+#define CCR_SDC_DCLK        (0 << 2)
+#define CCR_LCD_EXTCLK      (2 << 0) /* LCD clock select */
+#define CCR_LCD_MCLK        (1 << 0)
+#define CCR_LCD_HCLK        (0 << 0)
+
+#define CSR_PLL_PRESCALE    (1 << 9)
+#define CSR_PCIE_MODE1      (1 << 8)
+#define CSR_PCIE_MODE0      (1 << 7)
+#define CSR_DBG_SW          (1 << 6)
+#define CSR_DBG_EN          (1 << 5)
+#define CSR_NAND_LP         (1 << 4)         /* NAND: Large Page */
+#define CSR_NAND_AL(x)      (((x) >> 2) & 3) /* NAND: Address Length */
+#define CSR_NAND_16X        (1 << 1)         /* NAND: 16-bits */
+#define CSR_SPIBOOT         (1 << 0)         /* Boot from SPI(1)/NAND(0) */
+
+#endif
diff --git a/arch/arm/include/asm/arch-a369/ahbc.h b/arch/arm/include/asm/arch-a369/ahbc.h
new file mode 100644
index 0000000..30e6724
--- /dev/null
+++ b/arch/arm/include/asm/arch-a369/ahbc.h
@@ -0,0 +1,22 @@ 
+/*
+ * arch/arm/include/asm/arch-a369/ahbc.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_AHBC_H
+#define __ASM_ARCH_AHBC_H
+
+struct a369ahbc_regs {
+	uint32_t slave[32];/* Slave Device Configurations */
+	uint32_t priority; /* Priority */
+	uint32_t idle_cnt; /* IDLE Counter */
+	uint32_t control;  /* Control Register */
+	uint32_t revision; /* Revision ID */
+	uint32_t cpusao;   /* CPUS (FA606TE) Address Offset */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-a369/hardware.h b/arch/arm/include/asm/arch-a369/hardware.h
new file mode 100644
index 0000000..5b7695d
--- /dev/null
+++ b/arch/arm/include/asm/arch-a369/hardware.h
@@ -0,0 +1,86 @@ 
+/*
+ * arch/arm/include/asm/arch-a369/hardware.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+
+#define CONFIG_DRAM_BASE            0x10000000
+
+#define CONFIG_SRAM_BASE            0xA0000000
+#define CONFIG_SRAM_SIZE            0x00008000
+
+#define CONFIG_SCU_BASE             0x92000000
+#define CONFIG_DDR_BASE             0x93100000
+#define CONFIG_AHB_BASE             0x94000000
+#define CONFIG_SMC_BASE             0x94800000
+#define CONFIG_AHBC2_BASE           0x94200000
+
+/*
+ * Timer
+ */
+#define CONFIG_FTPWMTMR010_BASE     0x92300000
+#define CONFIG_FTPWMTMR010_IRQ      8
+
+/*
+ * UART
+ */
+#define CONFIG_FTUART010_BASE       0x92B00000
+
+/*
+ * Interrupt
+ */
+#define CONFIG_FTINTC020_BASE0      0x90100000
+#define CONFIG_FTINTC020_BASE1      0x96000000
+
+/*
+ * I2C
+ */
+#define CONFIG_FTI2C010_BASE0       0x92900000
+#define CONFIG_FTI2C010_BASE1       0x92A00000
+#define CONFIG_FTI2C010_BASE        CONFIG_FTI2C010_BASE0
+
+/*
+ * WatchDog
+ */
+#define CONFIG_FTWDT010_BASE        0x92200000
+
+/*
+ * NIC
+ */
+#define CONFIG_FTGMAC100_BASE       0x90C00000
+
+/*
+ * SPI
+ */
+#define CONFIG_FTSSP010_BASE        0x92700000
+
+/*
+ * NAND
+ */
+#define CONFIG_FTNANDC021_BASE      0x90200000
+
+/*
+ * LCD
+ */
+#define CONFIG_FTLCDC200_BASE       0x94A00000
+
+/*
+ * SD/MMC
+ */
+#define CONFIG_FTSDC010_BASE        0x90600000
+
+/*
+ * USB
+ */
+#define CONFIG_FUSBH200_BASE        0x90800000    /* FUSBH200 */
+#define CONFIG_FOTG210_BASE         0x90900000    /* FOTG210 */
+
+#endif
diff --git a/arch/arm/include/asm/arch-a369/scu.h b/arch/arm/include/asm/arch-a369/scu.h
new file mode 100644
index 0000000..763a015
--- /dev/null
+++ b/arch/arm/include/asm/arch-a369/scu.h
@@ -0,0 +1,212 @@ 
+/*
+ * arch/arm/include/asm/arch-a369/scu.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_SCU_H
+#define __ASM_ARCH_SCU_H
+
+struct a369scu_regs {
+	/* 0x000 ~ 0x0ff */
+	uint32_t idr;      /* ID Register */
+	uint32_t revr;     /* SCU revision id */
+	uint32_t hwcfg;    /* HW configuration strap */
+	uint32_t cpumcfr;  /* CPUM (master) freq. control */
+	uint32_t cr;       /* SCU control register */
+	uint32_t sr;       /* SCU status register */
+	uint32_t rsvd0[1];
+	uint32_t osccr;    /* OSC control register */
+	uint32_t pllcr;    /* PLL1 control register */
+	uint32_t dllcr;    /* DLL control register */
+	uint32_t hclkgr;   /* HCLK gating register */
+	uint32_t pclkgr;   /* PCLK gating register */
+	uint32_t rsvd1[52];
+
+	/* 0x100 ~ 0x1ff */
+	uint32_t spr[16];  /* Scratchpad register */
+	uint32_t rsvd2[48];
+
+	/* 0x200 ~ 0x2ff */
+	uint32_t gpmux;    /* General PINMUX */
+	uint32_t ehwcfg;   /* Extended HW configuration strap */
+	uint32_t rsvd3[8];
+	uint32_t sccfg[2]; /* Special clock configuration */
+	uint32_t scer;     /* Special clock enable register */
+	uint32_t rsvd;
+	uint32_t mfpmux[2];/* Multi-function pinmux */
+	uint32_t dcsrcr[2];/* Driving cap. & Slew rate control */
+	uint32_t rsvd4[3];
+	uint32_t dccr;     /* Delay chain control register */
+	uint32_t pcr;      /* Power control register */
+};
+
+/* HW configuration strap */
+#define HWCFG_PLL1NS(x)   (((x) >> 5) & 0x3f)
+#define HWCFG_CPUM_MUL(x) ((((x) >> 3) & 0x3) > 2 ? 2 : (((x) >> 3) & 0x3))
+#define HWCFG_DLL_OFF     (1 << 2)
+#define HWCFG_PLL_OFF     (1 << 1)
+#define HWCFG_OSCHCNT_OFF (1 << 0)
+
+/* Extended HW configuration strap */
+#define EHWCFG_AST         (1 << 15)
+#define EHWCFG_DBG         (1 << 14)
+#define EHWCFG_DBGBYSW     (1 << 13)
+#define EHWCFG_SATA_HOST   (1 << 12)
+#define EHWCFG_PCIE_RC     (1 << 11)
+#define EHWCFG_NAND_BK(x)  (((x) >> 9) & 0x3)
+#define EHWCFG_NAND_BK16   (0 << 9) /* 16 page per block */
+#define EHWCFG_NAND_BK32   (1 << 9) /* 32 page per block */
+#define EHWCFG_NAND_BK64   (2 << 9) /* 64 page per block */
+#define EHWCFG_NAND_BK128  (3 << 9) /* 128 page per block */
+#define EHWCFG_NAND_PS(x)  (((x) >> 7) & 0x3)
+#define EHWCFG_NAND_PS512  (0 << 7) /* 512 bytes per page */
+#define EHWCFG_NAND_PS2K   (1 << 7) /* 2048 bytes per page */
+#define EHWCFG_NAND_PS4K   (2 << 7) /* 4096 bytes per page */
+#define EHWCFG_NAND_AC(x)  (((x) >> 5) & 0x3)
+#define EHWCFG_NAND_AC3    (0 << 5) /* addr cycle = 3 */
+#define EHWCFG_NAND_AC4    (1 << 5) /* addr cycle = 4 */
+#define EHWCFG_NAND_AC5    (2 << 5) /* addr cycle = 5 */
+#define EHWCFG_NAND_16X    (1 << 4) /* NAND: 16bit mode */
+#define EHWCFG_EXTCPU      (1 << 2) /* external cpu mode */
+#define EHWCFG_BOOT_NAND   (0 << 0) /* boot from nand */
+#define EHWCFG_BOOT_SPI    (1 << 0) /* boot from spi */
+#define EHWCFG_BOOT_NOR    (2 << 0) /* boot from nor */
+
+/* General PINMUX */
+#define GPMUX_PLLGMAC      (1 << 15) /* PLL = GMAC PLL(PLL2) */
+#define GPMUX_EXTIRQ       (1 << 14) /* re-direct irq to external cpu */
+#define GPMUX_CS0REL       (1 << 13) /* release CS0 memory space */
+#define GPMUX_IOEN         (1 << 12) /* IO output enable */
+#define GPMUX_CPUS_START   (1 << 11) /* start slave cpu (fa606te) */
+#define GPMUX_SATA_RESET   (1 << 8)
+#define GPMUX_PDD          (1 << 7)  /* power-down detection enable */
+#define GPMUX_USBH_ALIVE   (1 << 6)
+#define GPMUX_USBH_PHYOSC  (1 << 5)
+#define GPMUX_OTG_ALIVE    (1 << 4)
+#define GPMUX_OTG_PHYOSC   (1 << 3)
+#define GPMUX_IRQMASK1     (1 << 2)
+#define GPMUX_IRQMASK0     (1 << 1)
+#define GPMUX_RESET        (1 << 0)
+
+#define GPMUX_DEFAULT      0x1078 /* USB keep alive + IO output */
+
+/* HCLK gating register */
+#define HCLKGR_CPUM        (1 << 31)
+#define HCLKGR_CPUS        (1 << 30)
+#define HCLKGR_AHBTSIF     (1 << 28)
+#define HCLKGR_AHBC3       (1 << 27)
+#define HCLKGR_AHBC2       (1 << 26)
+#define HCLKGR_AHBC1       (1 << 25)
+#define HCLKGR_APBBRG      (1 << 24)
+#define HCLKGR_NANDC       (1 << 23)
+#define HCLKGR_SMC         (1 << 22)
+#define HCLKGR_DMAC1       (1 << 21)
+#define HCLKGR_DMAC0       (1 << 20)
+#define HCLKGR_H264        (1 << 19)
+#define HCLKGR_MPEG4       (1 << 18)
+#define HCLKGR_2DGRA       (1 << 17)
+#define HCLKGR_LCD         (1 << 16)
+#define HCLKGR_ISP         (1 << 15)
+#define HCLKGR_AES         (1 << 14)
+#define HCLKGR_GMAC        (1 << 13)
+#define HCLKGR_SATAH       (1 << 12)
+#define HCLKGR_SATAD       (1 << 11)
+#define HCLKGR_PCIE        (1 << 10)
+#define HCLKGR_USBH        (1 << 9)
+#define HCLKGR_OTG         (1 << 8)
+#define HCLKGR_SD1         (1 << 7)
+#define HCLKGR_SD0         (1 << 6)
+#define HCLKGR_IDE         (1 << 5)
+#define HCLKGR_EM1         (1 << 4)
+#define HCLKGR_EM0         (1 << 3)
+#define HCLKGR_IRQ1        (1 << 2)
+#define HCLKGR_IRQ0        (1 << 1)
+#define HCLKGR_SCU         (1 << 0)
+
+/* Special clock configuration */
+#define SCCFG0_SATA_25M       (1 << 29)
+#define SCCFG0_SATA_OFF       (1 << 28)
+#define SCCFG0_GMAC_CLK_IO    (1 << 27)
+#define SCCFG0_GMAC_PLL_OFF   (1 << 26)
+#define SCCFG0_GMAC_PLL_NS(x) (((x) & 0x3f) << 20)
+#define SCCFG0_ISP_BFREQ(x)   (((x) & 0xf) << 16)
+#define SCCFG0_ISP_AFREQ(x)   (((x) & 0xf) << 12)
+#define SCCFG0_IDE_FREQ(x)    (((x) & 0xf) << 8)
+#define SCCFG0_EXTAHB_FREQ(x) (((x) & 0xf) << 4)
+#define SCCFG0_EXTAHB_MASK    0xf0
+#define SCCFG0_LCD_SCK_AHB    (0 << 2) /* LCD scalar clock source */
+#define SCCFG0_LCD_SCK_APB    (1 << 2)
+#define SCCFG0_LCD_SCK_EXT    (2 << 2)
+#define SCCFG0_LCD_CK_AHB     (0 << 0) /* LCD clock source */
+#define SCCFG0_LCD_CK_APB     (1 << 0)
+#define SCCFG0_LCD_CK_EXT     (2 << 0)
+
+#define SCCFG0_DEFAULT        0x26877330
+
+#define SCCFG1_SD1_CK_2AHB    (0 << 18) /* SD1 clock source */
+#define SCCFG1_SD1_CK_3APB    (1 << 18) /* SD1 clock source */
+#define SCCFG1_SD1_CK_AHB     (2 << 18) /* SD1 clock source */
+#define SCCFG1_SD0_CK_2AHB    (0 << 16) /* SD0 clock source */
+#define SCCFG1_SD0_CK_3APB    (1 << 16) /* SD0 clock source */
+#define SCCFG1_SD0_CK_AHB     (2 << 16) /* SD0 clock source */
+#define SCCFG1_SSP1_CK_EXT    (1 << 12) /* SSP1 clock source */
+#define SCCFG1_SSP1_FREQ(x)   (((x) & 0xf) << 8)
+#define SCCFG1_SSP0_CK_EXT    (1 << 4)  /* SSP0 clock source */
+#define SCCFG1_SSP0_FREQ(x)   (((x) & 0xf) << 0)
+
+#define SCCFG1_DEFAULT \
+	(SCCFG1_SD1_CK_AHB | SCCFG1_SD0_CK_AHB \
+	| SCCFG1_SSP1_FREQ(0xA) | SCCFG1_SSP0_FREQ(0xA))
+
+/* Special clock enable register */
+#define SCER_GMAC125M  (1 << 13)
+#define SCER_LCDSC     (1 << 12) /* LCD scalar clock */
+#define SCER_LCD       (1 << 11)
+#define SCER_ISPB      (1 << 10)
+#define SCER_ISPA      (1 << 9)
+#define SCER_IDE       (1 << 8)
+#define SCER_EXTAHB    (1 << 7)
+#define SCER_DDRD      (1 << 6)
+#define SCER_DDRF      (1 << 5)
+#define SCER_SD1       (1 << 4)
+#define SCER_SD0       (1 << 3)
+#define SCER_SSP1      (1 << 2)
+#define SCER_SSP0      (1 << 1)
+#define SCER_TSC       (1 << 0)
+
+/* Multi-function pinmux register */
+#define MFPMUX0_EBI(x)    (((x) & 0x3) << 10)
+#define MFPMUX0_LCD(x)    (((x) & 0x3) << 8)
+#define MFPMUX0_TS(x)     (((x) & 0x3) << 6)
+#define MFPMUX0_ISP(x)    (((x) & 0x3) << 4)
+#define MFPMUX0_SATA(x)   (((x) & 0x3) << 2)
+#define MFPMUX0_EXTAHB(x) (((x) & 0x3) << 0)
+
+#define MFPMUX0_DEFAULT   0x241 /* SD0 disabled, SD1 enabled */
+
+#define MFPMUX1_KBC(x)    (((x) & 0x3) << 20)
+#define MFPMUX1_GPIO0(x)  (((x) & 0x3) << 18)
+#define MFPMUX1_I2C1(x)   (((x) & 0x3) << 16)
+#define MFPMUX1_PWM1(x)   (((x) & 0x3) << 14)
+#define MFPMUX1_PWM0(x)   (((x) & 0x3) << 12)
+#define MFPMUX1_GMAC(x)   (((x) & 0x3) << 10)
+#define MFPMUX1_SSP1(x)   (((x) & 0x3) << 8)
+#define MFPMUX1_SSP0(x)   (((x) & 0x3) << 6)
+#define MFPMUX1_UART3(x)  (((x) & 0x3) << 4)
+#define MFPMUX1_UART2(x)  (((x) & 0x3) << 2)
+#define MFPMUX1_UART1(x)  (((x) & 0x3) << 0)
+
+/* PLL1 control register */
+#define PLLCR_NS(x)    (((x) >> 24) & 0x3f)
+#define PLLCR_STABLE   (1 << 1)
+#define PLLCR_OFF      (1 << 0)
+
+/* DLL control register */
+#define DLLCR_STABLE   (1 << 1)
+#define DLLCR_ON       (1 << 0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-faraday/clock.h b/arch/arm/include/asm/arch-faraday/clock.h
new file mode 100644
index 0000000..6c10415
--- /dev/null
+++ b/arch/arm/include/asm/arch-faraday/clock.h
@@ -0,0 +1,29 @@ 
+/*
+ * asm/arch-faraday/clock.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_FARADAY_CLOCK_H
+#define _ASM_ARCH_FARADAY_CLOCK_H
+
+/* Clock identifiers */
+enum clk_id {
+	SYS_CLK,
+	AHB_CLK,
+	APB_CLK,
+	CPU_CLK,
+	I2C_CLK,
+	MMC_CLK,
+	SDC_CLK,
+	SPI_CLK,
+	SSP_CLK,
+};
+
+void  clock_init(void);
+ulong clock_get_rate(enum clk_id id);
+
+#endif	/* _ASM_ARCH_FARADAY_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-faraday/interrupt.h b/arch/arm/include/asm/arch-faraday/interrupt.h
new file mode 100644
index 0000000..5eb406c
--- /dev/null
+++ b/arch/arm/include/asm/arch-faraday/interrupt.h
@@ -0,0 +1,17 @@ 
+/*
+ * asm/arch-faraday/interrupt.h
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_FARADAY_INTERRUPT_H
+#define _ASM_ARCH_FARADAY_INTERRUPT_H
+
+void irq_set_trigger(int irq, int edge, int low);
+void irq_enable(int irq);
+void irq_disable(int irq);
+
+#endif	/* _ASM_ARCH_FARADAY_INTERRUPT_H */
diff --git a/board/faraday/a360evb/Makefile b/board/faraday/a360evb/Makefile
new file mode 100644
index 0000000..233f6d3
--- /dev/null
+++ b/board/faraday/a360evb/Makefile
@@ -0,0 +1,29 @@ 
+#
+# (C) Copyright 2013 Faraday Technology
+# Dante Su <dantesu@faraday-tech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= board.o clock.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/faraday/a360evb/board.c b/board/faraday/a360evb/board.c
new file mode 100644
index 0000000..d622579
--- /dev/null
+++ b/board/faraday/a360evb/board.c
@@ -0,0 +1,71 @@ 
+/*
+ * board/faraday/a360evb/board.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <nand.h>
+#include <netdev.h>
+#include <asm/arch/scu.h>
+#include <faraday/ftsdc010.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct a360scu_regs *scu = (void __iomem *)CONFIG_SCU_BASE;
+
+/*
+ * pinmux
+ */
+static void pinmux_init(void)
+{
+	writel(0x00555500, &scu->iomcr[3]);
+	setbits_le32(&scu->iomcr[0], 0x800002AA);
+	setbits_le32(&scu->iomcr[1], 0x82AAAAAA);
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+
+int board_early_init_f(void)
+{
+	pinmux_init();
+	clock_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_SDRAM_SIZE;
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+	return ftmac110_initialize(bd);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FTSDC010
+	return ftsdc010_mmc_init(0);
+#else
+	return 0;
+#endif
+}
diff --git a/board/faraday/a360evb/clock.c b/board/faraday/a360evb/clock.c
new file mode 100644
index 0000000..a100a44
--- /dev/null
+++ b/board/faraday/a360evb/clock.c
@@ -0,0 +1,71 @@ 
+/*
+ * board/faraday/a360evb/clock.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/pmu.h>
+#include <asm/arch-faraday/clock.h>
+
+static struct a360scu_regs *scu = (void __iomem *)CONFIG_SCU_BASE;
+static struct a360pmu_regs *pmu = (void __iomem *)CONFIG_PMU_BASE;
+
+static inline ulong clk_get_rate_sys(void)
+{
+	return 40000000; /* 40 MHz */
+}
+
+static inline ulong clk_get_rate_ahb(void)
+{
+	return clk_get_rate_sys() * ((readl(&pmu->pdcr) >> 3) & 0x3f) / 8;
+}
+
+static inline ulong clk_get_rate_apb(void)
+{
+	return clk_get_rate_ahb() >> 1;
+}
+
+static inline ulong clk_get_rate_cpu(void)
+{
+	uint32_t s = readl(&scu->csr);
+	uint32_t p = readl(&pmu->pmr);
+	ulong clk = clk_get_rate_ahb();
+	ulong mul = (s & CSR_PLL_PRESCALE) ? 2 : 4;
+
+	return (p & PMR_TURBO) ? (clk * mul) : clk;
+}
+
+ulong clock_get_rate(enum clk_id id)
+{
+	switch (id) {
+	case SYS_CLK:
+		return clk_get_rate_sys();
+	case AHB_CLK:
+		return clk_get_rate_ahb();
+	case APB_CLK:
+		return clk_get_rate_apb();
+	case CPU_CLK:
+		return clk_get_rate_cpu();
+	case I2C_CLK:
+		return clk_get_rate_apb();
+	case MMC_CLK:
+	case SDC_CLK:
+		return clk_get_rate_ahb();
+	case SPI_CLK:
+	case SSP_CLK:
+		return clk_get_rate_apb();
+	default:
+		return 0;
+	}
+}
+
+void clock_init(void)
+{
+	gd->arch.timer_rate_hz = clk_get_rate_apb();
+}
diff --git a/board/faraday/a360evb/config.mk b/board/faraday/a360evb/config.mk
new file mode 100644
index 0000000..bbc18c8
--- /dev/null
+++ b/board/faraday/a360evb/config.mk
@@ -0,0 +1,17 @@ 
+#
+# (C) Copyright 2013 Faraday Technology
+# Dante Su <dantesu@faraday-tech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+#########################################################################
+
+ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+#ifeq ($(ENV),NAND)
+#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+#else
+#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+#endif
diff --git a/board/faraday/a360evb/lowlevel_init.S b/board/faraday/a360evb/lowlevel_init.S
new file mode 100644
index 0000000..90480aa
--- /dev/null
+++ b/board/faraday/a360evb/lowlevel_init.S
@@ -0,0 +1,16 @@ 
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc,lr
diff --git a/board/faraday/a369evb/Makefile b/board/faraday/a369evb/Makefile
new file mode 100644
index 0000000..233f6d3
--- /dev/null
+++ b/board/faraday/a369evb/Makefile
@@ -0,0 +1,29 @@ 
+#
+# (C) Copyright 2013 Faraday Technology
+# Dante Su <dantesu@faraday-tech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= board.o clock.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/faraday/a369evb/board.c b/board/faraday/a369evb/board.c
new file mode 100644
index 0000000..b00d2f4
--- /dev/null
+++ b/board/faraday/a369evb/board.c
@@ -0,0 +1,175 @@ 
+/*
+ * board/faraday/a369evb/board.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <spi.h>
+#include <nand.h>
+#include <netdev.h>
+#include <malloc.h>
+
+#include <asm/arch/scu.h>
+#include <faraday/ftsmc020.h>
+#include <faraday/ftlcdc200.h>
+#include <faraday/ftsdc010.h>
+#include <faraday/ftnandc021.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct ftsmc020 *smc = (void __iomem *)CONFIG_SMC_BASE;
+static struct a369scu_regs *scu = (void __iomem *)CONFIG_SCU_BASE;
+static struct ftlcdc200_regs *lcd = (void __iomem *)CONFIG_FTLCDC200_BASE;
+
+/* System Control Uint (pinmux) */
+static void scu_init(void)
+{
+	/* If it's an external CPU */
+	if (readl(&scu->ehwcfg) & EHWCFG_EXTCPU) {
+		writel(HCLKGR_CPUM | HCLKGR_CPUS | HCLKGR_ISP,
+			&scu->hclkgr);
+		setbits_le32(&scu->gpmux, GPMUX_EXTIRQ);
+	} else {
+#ifdef CONFIG_SUPP_EXTAHB
+		/* Enable external AHB */
+		writel(HCLKGR_CPUS, &scu->hclkgr);
+		writel(GPMUX_DEFAULT, &scu->gpmux);
+		clrbits_le32(&scu->sccfg[0], SCCFG0_EXTAHB_MASK);
+		setbits_le32(&scu->sccfg[0], SCCFG0_EXTAHB_FREQ(8));
+#else
+		/* Enable SD1 */
+		writel(MFPMUX0_DEFAULT, &scu->mfpmux[0]);
+#endif
+	}
+
+	/* Clock Setup: SD = AHB, SSP = APB (SPI mode) */
+	writel(SCCFG1_DEFAULT, &scu->sccfg[1]);
+
+	/* Enable LCD for I2C/TVEncode work-around */
+	/* ... Clock DIV=32 */
+	writel(PCR_DIV(32), &lcd->pcr);
+	/* ... Enable LCD */
+	writel(FER_EN | FER_ON, &lcd->fer);
+}
+
+/*
+ * Static Memory Controller (NOR Flash)
+ */
+static void smc_init(void)
+{
+	/* 1. NOR flash */
+	/* Bank 0: base=0x00000000, size=64MB, 16bits */
+	writel(FTSMC020_BANK_ENABLE | FTSMC020_BANK_BASE(0)
+		| FTSMC020_BANK_SIZE_64M | FTSMC020_BANK_MBW_16,
+		&smc->bank[0].cr);
+	/* Bank 0: worst timing */
+	writel(FTSMC020_TPR_WORST, &smc->bank[0].tpr);
+
+	/* 2. Unused Area */
+	writel(0, &smc->bank[1].cr);
+	writel(FTSMC020_TPR_WORST, &smc->bank[1].tpr);
+	writel(0, &smc->bank[2].cr);
+	writel(FTSMC020_TPR_WORST, &smc->bank[2].tpr);
+	writel(0, &smc->bank[3].cr);
+	writel(FTSMC020_TPR_WORST, &smc->bank[3].tpr);
+}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_early_init_f(void)
+{
+	scu_init();
+	smc_init();
+	clock_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_FARADAY;
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size  = CONFIG_SYS_SDRAM_SIZE;
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+	return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+#ifdef CONFIG_USB_ETHER
+	return usb_eth_initialize(bd);
+#elif defined(CONFIG_FTGMAC100)
+	return ftgmac100_initialize(bd);
+#endif
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_FTSDC010
+	return ftsdc010_mmc_init(0);
+#else
+	return 0;
+#endif
+}
+
+#ifdef CONFIG_SYS_NAND_SELF_INIT
+void board_nand_init(void)
+{
+	int alen, devnum = 0;
+	struct mtd_info *mtd = &nand_info[devnum];
+	struct nand_chip *chip;
+	uint32_t iobase = CONFIG_SYS_NAND_BASE;
+	uint32_t ehwcfg = readl(&scu->ehwcfg);
+
+	chip = calloc(1, sizeof(*chip));
+	if (!chip)
+		return;
+	mtd->priv = chip;
+
+	/* page size */
+	switch (EHWCFG_NAND_PS(ehwcfg)) {
+	case 0:
+		chip->page_shift = 9;	/* 512 */
+		break;
+	case 1:
+		chip->page_shift = 11;	/* 2048 */
+		break;
+	default:
+		chip->page_shift = 12;	/* 4096 */
+		break;
+	}
+
+	/* block size */
+	chip->phys_erase_shift = chip->page_shift + 4
+		+ EHWCFG_NAND_BK(ehwcfg);
+
+	/* address length/cycle */
+	alen = 3 + EHWCFG_NAND_AC(ehwcfg);
+
+	if (ftnandc021_init(chip, iobase, alen))
+		goto bni_err;
+
+	if (nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS))
+		goto bni_err;
+
+	nand_register(devnum);
+
+	return;
+
+bni_err:
+	free(chip);
+}
+#endif /* #ifdef CONFIG_SYS_NAND_SELF_INIT */
diff --git a/board/faraday/a369evb/clock.c b/board/faraday/a369evb/clock.c
new file mode 100644
index 0000000..890aecc
--- /dev/null
+++ b/board/faraday/a369evb/clock.c
@@ -0,0 +1,81 @@ 
+/*
+ * board/faraday/a369evb/clock.c
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/scu.h>
+#include <asm/arch-faraday/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct a369scu_regs *scu = (void __iomem *)CONFIG_SCU_BASE;
+
+static inline ulong clk_get_rate_sys(void)
+{
+	return 33000000; /* 33 MHz */
+}
+
+static inline ulong clk_get_rate_ahb(void)
+{
+	return (clk_get_rate_sys() * PLLCR_NS(readl(&scu->pllcr))) >> 3;
+}
+
+static inline ulong clk_get_rate_apb(void)
+{
+	return clk_get_rate_ahb() >> 1;
+}
+
+static inline ulong clk_get_rate_cpu(void)
+{
+	ulong clk = clk_get_rate_ahb();
+
+#ifndef CONFIG_A369_FA606TE_PLATFORM
+	/* If it's an internal CPU */
+	if (readl(&scu->ehwcfg) & EHWCFG_EXTCPU)
+		return clk;
+	/*
+	 * Since the master would stop immediately after
+	 * kicking off slave cpu, so we could check the
+	 * GPMUX_CPUS_START to determine if it's a master.
+	 */
+	if (!(readl(&scu->gpmux) & GPMUX_CPUS_START))
+		clk = clk << HWCFG_CPUM_MUL(readl(&scu->hwcfg));
+#endif
+
+	return clk;
+}
+
+ulong clock_get_rate(enum clk_id id)
+{
+	switch (id) {
+	case SYS_CLK:
+		return clk_get_rate_sys();
+	case AHB_CLK:
+		return clk_get_rate_ahb();
+	case APB_CLK:
+		return clk_get_rate_apb();
+	case CPU_CLK:
+		return clk_get_rate_cpu();
+	case I2C_CLK:
+		return clk_get_rate_apb();
+	case MMC_CLK:
+	case SDC_CLK:
+		return clk_get_rate_ahb();
+	case SPI_CLK:
+	case SSP_CLK:
+		return clk_get_rate_apb();
+	default:
+		return 0;
+	}
+}
+
+void clock_init(void)
+{
+	gd->arch.timer_rate_hz = clk_get_rate_apb();
+}
diff --git a/board/faraday/a369evb/config.mk b/board/faraday/a369evb/config.mk
new file mode 100644
index 0000000..bbc18c8
--- /dev/null
+++ b/board/faraday/a369evb/config.mk
@@ -0,0 +1,17 @@ 
+#
+# (C) Copyright 2013 Faraday Technology
+# Dante Su <dantesu@faraday-tech.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+#########################################################################
+
+ALL += $(obj)u-boot.img
+
+# Environment variables in NAND
+#ifeq ($(ENV),NAND)
+#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_NAND
+#else
+#PLATFORM_RELFLAGS += -DCONFIG_ENV_IS_IN_FLASH
+#endif
diff --git a/board/faraday/a369evb/lowlevel_init.S b/board/faraday/a369evb/lowlevel_init.S
new file mode 100644
index 0000000..e7cbcad
--- /dev/null
+++ b/board/faraday/a369evb/lowlevel_init.S
@@ -0,0 +1,119 @@ 
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <common.h>
+#include <version.h>
+
+	.macro	_v3_mw32
+
+	ldr r0, =0x1008
+	ldr r3, =0x1108
+_v3_mw32_loop:
+	cmp   r0, r3
+	movhs r1, #0
+	ldrlo r1, [r0, #0]
+	ldrlo r2, [r0, #4]
+	teq   r1, #0
+	strne r2, [r1, #0]
+	addne r0, #8
+	bne   _v3_mw32_loop
+
+	.endm	/* _v3_mw32 */
+
+	.macro	_sdram_enable
+
+	/* Clear SDRAM CKE, GPIO Hold, READ Hold */
+	ldr r0, =CONFIG_SCU_BASE
+	mov r1, #7
+	str r1, [r0, #0x14]
+
+	/* Wait until sdram ready */
+	ldr r0, =CONFIG_DDR_BASE
+_sdram_wait:
+	ldr r1, [r0, #0x04]
+	teq r1, #0x100
+	bne _sdram_wait
+
+	.endm	/* _sdram_enable */
+
+/* Set up the platform, once the cpu has been initialized */
+.globl lowlevel_init
+lowlevel_init:
+	/* Check image header */
+	ldr   r1, =0x1000
+	ldr   r0, [r1, #0]
+	ldr   r1, =0x00484946	/* "FIH\0" */
+	ldr   r2, =0x33333639	/* "3369" */
+	teq   r0, r1
+	teqne r0, r2
+	bne _exit
+	_v3_mw32
+	_sdram_enable
+
+#if 1
+	/* Create a shadow copy onto SDRAM (limited to 512K) */
+	mov	r0, #0               /* r0 <- start of source */
+	ldr	r1, =CONFIG_AHB_BASE
+	ldr r2, [r1,#0x18]
+	bic r1, r2, #0x000f0000  /* r1 <- SDRAM base */
+	mov	r2, #0x80000         /* r2 <- source end address (512KB) */
+
+_copy_loop:
+	ldmia	r0!, {r3-r10} /* copy from source address [r0] */
+	stmia	r1!, {r3-r10} /* copy to   target address [r1] */
+	cmp	r0, r2            /* until source end addreee [r2] */
+	ble	_copy_loop
+#else
+	/* Adjust lr(r14) to the remapped address */
+	ldr r0, =CONFIG_AHB_BASE
+	ldr r1, [r0,#0x18]    /* r1 = AHB slave 6 */
+	bic r1, r1, #0xff000000
+	bic r1, r1, #0x00f00000
+	lsr r1, r1, #16
+	add r1, r1, #20
+	mov r2, #1
+	lsl r2, r2, r1
+	add lr, lr, r2
+#endif
+
+	/* AHB remap */
+	mov r0, #0
+	ldr r1, =CONFIG_AHB_BASE
+	ldr r2, =CONFIG_DDR_BASE
+	/* magic (r5) = REG32(0x00) XOR 0xFFFFFFFF */
+	ldr r5, [r0, #0]
+	ldr r3, =0xffffffff
+	eor r5, r5, r3
+	/* r3 = REG32(CONFIG_IOBASE_DDR + 0x10) & 0x00FFFFFF */
+	ldr r3, [r2, #0x10]
+	bic r3, #0xff000000
+	/* r4 = 0x00100f01 */
+	ldr r4, =0x00100f01
+
+	/*
+	 * invalidate i-cache all to make sure the codes bellow
+	 * to be fetched into a single 32-bytes cache line
+	 */
+	mcr p15, 0, r0, c7, c5, 0
+
+	.align 5
+
+	str r3, [r2, #0x10] /* REG32(CONFIG_IOBASE_DDR + 0x10) &= 0x00FFFFFF */
+	str r4, [r1, #0x88] /* REG32(CONFIG_IOBASE_AHB + 0x88)  = 0x00100F01 */
+
+_remap_wait:
+	str r5, [r0, #0]
+	ldr r1, [r0, #0]
+	teq r1, r5
+	bne _remap_wait		/* while(magic != REG32(addr)) */
+
+_exit:
+	mov	pc, lr
diff --git a/boards.cfg b/boards.cfg
index 944ed4c..ed45524 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -72,6 +72,9 @@  mini2440                     arm         arm920t     mini2440            friendl
 VCMA9                        arm         arm920t     vcma9               mpl            s3c24x0
 smdk2410                     arm         arm920t     -                   samsung        s3c24x0
 omap1510inn                  arm         arm925t     -                   ti
+a360                         arm         faraday     a360evb             faraday        a360
+a369                         arm         faraday     a369evb             faraday        a369
+a369_fa606te                 arm         faraday     a369evb             faraday        a369
 integratorap_cm926ejs        arm         arm926ejs   integrator          armltd         -           integratorap:CM926EJ_S
 integratorcp_cm926ejs        arm         arm926ejs   integrator          armltd         -           integratorcp:CM924EJ_S
 aspenite                     arm         arm926ejs   -                   Marvell        armada100
diff --git a/include/common.h b/include/common.h
index dbebecf..ab9f0d2 100644
--- a/include/common.h
+++ b/include/common.h
@@ -95,6 +95,8 @@  typedef volatile unsigned char	vu_char;
 #include <asm/arch/hardware.h>
 #endif
 #ifdef CONFIG_FARADAY
+#include <asm/arch/hardware.h>
+#include <asm/arch-faraday/clock.h>
 #include <asm/arch-faraday/interrupt.h>
 #endif

diff --git a/include/configs/a360.h b/include/configs/a360.h
new file mode 100644
index 0000000..3ad0b8f
--- /dev/null
+++ b/include/configs/a360.h
@@ -0,0 +1,70 @@ 
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * Support for Faraday A360(FIE3360) boards.
+ * Tested on A360 EVB2 with 256MB SDRAM and 128MB nand flash.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+/* Support USB RNDIS Ethernet */
+/* #define CONFIG_SUPP_USB_RNDIS */
+
+/* Support interrupt */
+/* #define CONFIG_USE_IRQ */
+
+/* Disable MMU/D-CACHE */
+/* #define CONFIG_SYS_DCACHE_OFF */
+
+/*
+ * Memory Configuration
+ */
+#define CONFIG_NR_DRAM_BANKS        1
+#define CONFIG_SYS_SDRAM_BASE       0x00000000
+#define CONFIG_SYS_SDRAM_SIZE       SZ_64M
+
+#define CONFIG_SYS_MEMTEST_START    (CONFIG_SYS_SDRAM_BASE + SZ_16M)
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_SDRAM_BASE + SZ_32M)
+
+/* SPI Flash (FTSSP010 v1.18) */
+#define CONFIG_FTSSP010_GPIO_PIN    26
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/*
+ * USB Configuration
+ */
+#define CONFIG_USB_EHCI_BASE        CONFIG_FUSBH200_BASE
+#ifdef CONFIG_SUPP_USB_RNDIS
+# define CONFIG_USB_MAX_CONTROLLER_COUNT    1
+#else
+# define CONFIG_USB_MAX_CONTROLLER_COUNT    2
+# define CONFIG_USB_EHCI_BASE_LIST  \
+	{ CONFIG_FUSBH200_BASE, CONFIG_FOTG210_BASE }
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE             SZ_64K
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	/* Default network configuration */ \
+	"ethaddr=00:41:71:00:00:50\0" \
+	"serverip=10.0.0.128\0" \
+	"ipaddr=10.0.0.192\0"
+
+/*
+ * Faraday Common Configuration
+ */
+#include "faraday-common.h"
+
+#endif
diff --git a/include/configs/a369-common.h b/include/configs/a369-common.h
new file mode 100644
index 0000000..330639d
--- /dev/null
+++ b/include/configs/a369-common.h
@@ -0,0 +1,85 @@ 
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * Support for Faraday A369(FIE3369) boards.
+ * Tested on A369 EVB2 with 512MB SDRAM and 256MB nand flash.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_A369_COMMON_H
+#define __CONFIG_A369_COMMON_H
+
+#include <asm/hardware.h>
+
+/* A369 Platform Common Configuration */
+
+/* Memory Configuration */
+#define CONFIG_NR_DRAM_BANKS        1
+#define CONFIG_SYS_SDRAM_BASE       0x00000000
+#define CONFIG_SYS_SDRAM_SIZE       SZ_512M
+
+#define CONFIG_SYS_MEMTEST_START    (CONFIG_SYS_SDRAM_BASE + SZ_16M)
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_SDRAM_BASE + SZ_32M)
+
+/* Interrupt controler */
+#ifndef CONFIG_FTINTC020_BASE
+#define CONFIG_FTINTC020_BASE       CONFIG_FTINTC020_BASE0
+#endif
+
+/* NAND Flash */
+#define CONFIG_NAND_K9F4G08U0B_AC1  0x02240264
+#define CONFIG_NAND_K9F4G08U0B_AC2  0x42054209
+#define CONFIG_SYS_MAX_NAND_DEVICE  1 /* Max. num. of devices */
+#define CONFIG_SYS_FTNANDC021_TIMING \
+	{ CONFIG_NAND_K9F4G08U0B_AC1, CONFIG_NAND_K9F4G08U0B_AC2 }
+
+/* SPI Flash (FTSSP010 v1.18) */
+#define CONFIG_FTSSP010_GPIO_BASE   0x92600000 /* GPIO 1 */
+#define CONFIG_FTSSP010_GPIO_PIN    27
+
+/* NOR Flash */
+/*
+#define PHYS_FLASH_SIZE             SZ_64M
+#define CONFIG_SYS_FLASH_BASE       0x20000000
+#define CONFIG_SYS_FLASH_CFI_WIDTH  FLASH_CFI_16BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS  1
+#define CONFIG_SYS_MAX_FLASH_SECT   1024
+*/
+
+/* EEPROM */
+#define CONFIG_ENV_EEPROM_IS_ON_I2C
+
+/*
+ * USB Configuration
+ */
+#define CONFIG_USB_EHCI_BASE        CONFIG_FUSBH200_BASE
+#ifdef CONFIG_SUPP_USB_RNDIS
+# define CONFIG_USB_MAX_CONTROLLER_COUNT    1
+#else
+# define CONFIG_USB_MAX_CONTROLLER_COUNT    2
+# define CONFIG_USB_EHCI_BASE_LIST  \
+	{ CONFIG_FUSBH200_BASE, CONFIG_FOTG210_BASE }
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET           0x07FC0000
+#define CONFIG_ENV_OFFSET_REDUND    0x07FE0000
+#define CONFIG_ENV_SIZE             SZ_64K
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	/* Default network configuration */ \
+	"ethaddr=00:41:71:00:00:50\0" \
+	"serverip=10.0.0.128\0" \
+	"ipaddr=10.0.0.192\0"
+
+/*
+ * Faraday Common Configuration
+ */
+#include "faraday-common.h"
+
+#endif
diff --git a/include/configs/a369.h b/include/configs/a369.h
new file mode 100644
index 0000000..fd28629
--- /dev/null
+++ b/include/configs/a369.h
@@ -0,0 +1,47 @@ 
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * Support for Faraday A369(FIE3369) boards.
+ * Tested on A369 EVB2 with 512MB SDRAM and 256MB nand flash.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_A369_PLATFORM
+
+/* Support USB-EHCI */
+#define CONFIG_SUPP_EHCI_FARADAY
+
+/* Support external AHB */
+/* #define CONFIG_SUPP_EXTAHB */
+
+/* Support USB RNDIS Ethernet */
+/* #define CONFIG_SUPP_USB_RNDIS */
+
+/* Support VGA Console */
+/* #define CONFIG_SUPP_VGA_CONSOLE */
+
+/* Support interrupt */
+/* #define CONFIG_USE_IRQ */
+
+/* Disable MMU/D-CACHE */
+/* #define CONFIG_SYS_DCACHE_OFF */
+
+/* Support runtime switching to built-in slave core: FA606TE */
+#define CONFIG_CMD_FA606
+
+/* Autoboot */
+#define CONFIG_BOOTDELAY            3
+#define CONFIG_BOOTCOMMAND          "bootfa nand linux"
+
+/* Set interrupt controler to FTINCT020.0 */
+#define CONFIG_FTINTC020_BASE       CONFIG_FTINTC020_BASE0
+
+/* A369 common configuration */
+#include "a369-common.h"
+
+#endif
diff --git a/include/configs/a369_fa606te.h b/include/configs/a369_fa606te.h
new file mode 100644
index 0000000..521f14e
--- /dev/null
+++ b/include/configs/a369_fa606te.h
@@ -0,0 +1,40 @@ 
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * Support for Faraday A369(FIE3369) boards.
+ * Tested on A369 EVB2 with 512MB SDRAM and 256MB nand flash.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_A369_FA606TE_PLATFORM
+
+/* Support external AHB */
+/* #define CONFIG_SUPP_EXTAHB */
+
+/* Support USB RNDIS Ethernet */
+/* #define CONFIG_SUPP_USB_RNDIS */
+
+/* Support VGA Console */
+/* #define CONFIG_SUPP_VGA_CONSOLE */
+
+/* Support interrupt */
+/* #define CONFIG_USE_IRQ */
+
+/* Disable MMU/D-CACHE */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Disable I-CACHE */
+#define CONFIG_SYS_ICACHE_OFF
+
+/* Set interrupt controler to FTINCT020.1 */
+#define CONFIG_FTINTC020_BASE       CONFIG_FTINTC020_BASE1
+
+/* A369 common configuration */
+#include "a369-common.h"
+
+#endif
diff --git a/include/configs/faraday-common.h b/include/configs/faraday-common.h
new file mode 100644
index 0000000..7f97042
--- /dev/null
+++ b/include/configs/faraday-common.h
@@ -0,0 +1,242 @@ 
+/*
+ * (C) Copyright 2013 Faraday Technology
+ * Dante Su <dantesu@faraday-tech.com>
+ *
+ * Support for Faraday SoC platforms.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_FARADAY_COMMON_H
+#define __CONFIG_FARADAY_COMMON_H
+
+#include <asm/mach-types.h>
+
+#ifndef MACH_TYPE_FARADAY
+#define MACH_TYPE_FARADAY           758
+#endif
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+#define CONFIG_SYS_TEXT_BASE        0x00800000
+#define CONFIG_BOARD_EARLY_INIT_F   1
+
+/*
+ * Initial stack pointer: GENERATED_GBL_DATA_SIZE in internal SRAM.
+ * Inside the board_init_f, the gd is first assigned to
+ * (CONFIG_SYS_INIT_SP_ADDR) & ~0x07) and then relocated to DRAM
+ * while calling relocate_code.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_STACKSIZE            SZ_512K
+#define CONFIG_STACKSIZE_IRQ        SZ_32K
+#define CONFIG_STACKSIZE_FIQ        SZ_32K
+
+#define CONFIG_SYS_MALLOC_LEN       SZ_8M
+#define CONFIG_SYS_MONITOR_LEN      SZ_512K
+
+/*
+ * CPU
+ */
+#define CONFIG_FARADAY
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifndef CONFIG_SYS_DCACHE_OFF
+# define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
+#endif
+
+/*
+ * Interrupt
+ */
+#if defined(CONFIG_USE_IRQ) && defined(CONFIG_FTI2C010_BASE)
+# define CONFIG_FTINTC020
+#endif
+
+/*
+ * Timer
+ */
+#define CONFIG_SYS_HZ               1000
+
+#ifdef CONFIG_FTTMR010_BASE
+# define CONFIG_FTTMR010
+#endif /* CONFIG_FTTMR010_BASE */
+
+#ifdef CONFIG_FTPWMTMR010_BASE
+# define CONFIG_FTPWMTMR010
+#endif /* CONFIG_FTPWMTMR010_BASE */
+
+/*
+ * Serial Info
+ */
+#ifdef CONFIG_FTUART010_BASE
+# define CONFIG_SYS_NS16550
+# define CONFIG_SYS_NS16550_SERIAL
+# ifndef CONFIG_SYS_NS16550_CLK
+#  define CONFIG_SYS_NS16550_CLK     18432000
+# endif
+# define CONFIG_SYS_NS16550_COM1     CONFIG_FTUART010_BASE
+# define CONFIG_SYS_NS16550_MEM32
+# define CONFIG_SYS_NS16550_REG_SIZE -4
+# define CONFIG_CONS_INDEX           1
+# define CONFIG_BAUDRATE             38400
+# undef  CONFIG_HWFLOW
+# undef  CONFIG_MODEM_SUPPORT
+#endif /* #ifdef CONFIG_FTUART010_BASE */
+
+/*
+ * NIC driver
+ */
+#ifdef CONFIG_FTMAC110_BASE
+# define CONFIG_FTMAC110
+#endif
+#ifdef CONFIG_FTGMAC100_BASE
+# define CONFIG_FTGMAC100
+# define CONFIG_FTGMAC100_EGIGA    /* Used by Ratbert's ftgmac100 only */
+# define CONFIG_PHY_GIGE /* Enable giga phy support for miiphyutil.c */
+#endif
+#if defined(CONFIG_FTMAC110) || defined(CONFIG_FTGMAC100)
+# define CONFIG_PHY_MAX_ADDR    32 /* Used by Ratbert's ftgmac100 only */
+# define CONFIG_RANDOM_MACADDR
+# define CONFIG_MII
+# define CONFIG_NET_MULTI
+# define CONFIG_NET_RETRY_COUNT 20
+# define CONFIG_DRIVER_ETHER
+# define CONFIG_CMD_MII
+# define CONFIG_CMD_PING
+#endif
+
+/*
+ * NOR Flash
+ */
+#ifdef CONFIG_SYS_FLASH_BASE
+# define CONFIG_SYS_FLASH_CFI
+# define CONFIG_FLASH_CFI_DRIVER
+# define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+# define CONFIG_CMD_IMLS
+# define CONFIG_CMD_FLASH
+#else
+# define CONFIG_SYS_NO_FLASH
+#endif /* !CONFIG_SYS_NO_FLASH */
+
+/*
+ * NAND Flash
+ */
+#ifdef CONFIG_FTNANDC021_BASE
+# define CONFIG_SYS_NAND_SELF_INIT
+# define CONFIG_NAND_FTNANDC021
+# define CONFIG_SYS_NAND_BASE           CONFIG_FTNANDC021_BASE
+# define CONFIG_MTD_NAND_VERIFY_WRITE
+# define CONFIG_CMD_NAND
+#endif
+
+/*
+ * MMC/SD
+ */
+#ifdef CONFIG_FTSDC010_BASE
+# define CONFIG_FTSDC010
+# define CONFIG_FTSDC010_SDIO /* The hardware core supports SDIO */
+# define CONFIG_MMC
+# define CONFIG_CMD_MMC
+# define CONFIG_GENERIC_MMC
+#endif
+
+/*
+ * USB EHCI
+ */
+#if defined(CONFIG_SUPP_EHCI_FARADAY) && (CONFIG_USB_MAX_CONTROLLER_COUNT > 0)
+# define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
+# define CONFIG_USB_EHCI
+# define CONFIG_USB_EHCI_FARADAY
+# define CONFIG_EHCI_IS_TDI
+# define CONFIG_CMD_USB
+# define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * USB Gadget
+ */
+#if defined(CONFIG_SUPP_USB_RNDIS) && defined(CONFIG_FOTG210_BASE)
+# define CONFIG_USB_GADGET
+# define CONFIG_USB_GADGET_FOTG210
+# define CONFIG_USB_GADGET_DUALSPEED
+# define CONFIG_USB_ETHER
+# define CONFIG_USB_ETH_RNDIS
+# define CONFIG_USBNET_DEV_ADDR     "00:41:71:00:00:55" /* U-Boot */
+# define CONFIG_USBNET_HOST_ADDR    "00:41:71:00:00:54" /* Host PC */
+#endif
+
+/*
+ * LCD
+ */
+#if defined(CONFIG_SUPP_VGA_CONSOLE) && defined(CONFIG_FTLCDC200_BASE)
+# define CONFIG_FTLCDC200
+# define CONFIG_FTLCDC200_800X480S_TPO
+# define LCD_BPP                    4 /* 16-bit per pixel */
+# define CONFIG_LCD
+#endif
+
+/*
+ * U-Boot General Configurations
+ */
+#define CONFIG_LZMA                 /* Support LZMA */
+#define CONFIG_VERSION_VARIABLE     /* Include version env variable */
+#ifndef CONFIG_SYS_LOAD_ADDR        /* Default load address */
+# define CONFIG_SYS_LOAD_ADDR       (CONFIG_SYS_SDRAM_BASE + SZ_1M)
+#endif
+/* Console Baud-Rate Table */
+#define CONFIG_SYS_BAUDRATE_TABLE   { 115200, 57600, 38400, 19200, 9600 }
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE           256
+/* Max number of command args */
+#define CONFIG_SYS_MAXARGS          32
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/*
+ * Shell
+ */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2  "$ "
+#define CONFIG_SYS_PROMPT           "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * FAT Filesystem
+ */
+#if defined(CONFIG_USB_STORAGE) || defined(CONFIG_MMC)
+# define CONFIG_DOS_PARTITION
+# define CONFIG_CMD_FAT
+#endif
+
+/*
+ * Linux kernel command line options
+ */
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/*
+ * Default Commands
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMD_AUTOSCRIPT   /* support autoscript */
+#define CONFIG_CMD_BDI          /* bdinfo */
+#define CONFIG_CMD_ECHO         /* echo arguments */
+#define CONFIG_CMD_ENV          /* printenv */
+#define CONFIG_CMD_MEMORY       /* md mm nm mw ... */
+#define CONFIG_CMD_NET          /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_RUN          /* run command in env variable */
+#define CONFIG_CMD_ELF          /* support ELF files */
+#ifndef CONFIG_ENV_IS_NOWHERE
+# define CONFIG_CMD_SAVEENV     /* saveenv */
+#endif
+
+#endif
diff --git a/include/faraday/ftsmc020.h b/include/faraday/ftsmc020.h
index 54120ab..89809b6 100644
--- a/include/faraday/ftsmc020.h
+++ b/include/faraday/ftsmc020.h
@@ -70,5 +70,6 @@  void ftsmc020_init(void);
 #define FTSMC020_TPR_WTC(x)	(((x) & 0x3) << 6)
 #define FTSMC020_TPR_AHT(x)	(((x) & 0x3) << 4)
 #define FTSMC020_TPR_TRNA(x)	(((x) & 0xf) << 0)
+#define FTSMC020_TPR_WORST	0x0f1ff3ff /* worst but safe */

 #endif	/* __FTSMC020_H */