Patchwork [U-Boot,1/2] usb: ehci-mx5: Remove unneeded write to cscmr1 register

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Submitter Fabio Estevam
Date July 26, 2013, 4:54 p.m.
Message ID <1374857668-28284-1-git-send-email-festevam@gmail.com>
Download mbox | patch
Permalink /patch/262221/
State Awaiting Upstream
Delegated to: Marek Vasut
Headers show

Comments

Fabio Estevam - July 26, 2013, 4:54 p.m.
From: Fabio Estevam <fabio.estevam@freescale.com>

Currently we have the following behavior in ehci_hcd_init()

- Read csmr1 register, clear bit 26 and then set bit 26.

However a little bit later we call set_usb_phy_clk() which clears bit 26, so
let's get rid of the unnecessary code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
 drivers/usb/host/ehci-mx5.c | 9 ---------
 1 file changed, 9 deletions(-)

Patch

diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index f43c38d..6178a1d 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -229,15 +229,6 @@  void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
 int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
 	struct usb_ehci *ehci;
-#ifdef CONFIG_MX53
-	struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR;
-	u32 reg;
-
-	reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26);
-	/* derive USB PHY clock multiplexer from PLL3 */
-	reg |= 1 << 26;
-	__raw_writel(reg, &sc_regs->cscmr1);
-#endif
 
 	set_usboh3_clk();
 	enable_usboh3_clk(1);