From patchwork Fri Jul 26 05:46:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 262059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 62FEF2C0110 for ; Fri, 26 Jul 2013 15:53:06 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752170Ab3GZFxF (ORCPT ); Fri, 26 Jul 2013 01:53:05 -0400 Received: from mail-db8lp0185.outbound.messaging.microsoft.com ([213.199.154.185]:59088 "EHLO db8outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752135Ab3GZFxD (ORCPT ); Fri, 26 Jul 2013 01:53:03 -0400 Received: from mail189-db8-R.bigfish.com (10.174.8.232) by DB8EHSOBE028.bigfish.com (10.174.4.91) with Microsoft SMTP Server id 14.1.225.22; Fri, 26 Jul 2013 05:53:01 +0000 Received: from mail189-db8 (localhost [127.0.0.1]) by mail189-db8-R.bigfish.com (Postfix) with ESMTP id 7A711D0021C; Fri, 26 Jul 2013 05:53:01 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz1de098h1de097h8275bhz2dh2a8h668h839he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1155h) Received: from mail189-db8 (localhost.localdomain [127.0.0.1]) by mail189-db8 (MessageSwitch) id 1374817978840086_19773; Fri, 26 Jul 2013 05:52:58 +0000 (UTC) Received: from DB8EHSMHS010.bigfish.com (unknown [10.174.8.227]) by mail189-db8.bigfish.com (Postfix) with ESMTP id BCDAF640045; Fri, 26 Jul 2013 05:52:58 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS010.bigfish.com (10.174.4.20) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 26 Jul 2013 05:52:57 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.136.1; Fri, 26 Jul 2013 05:52:43 +0000 Received: from freescale.com ([10.232.15.72]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with SMTP id r6Q5qcYg011353; Thu, 25 Jul 2013 22:52:39 -0700 Received: by freescale.com (sSMTP sendmail emulation); Fri, 26 Jul 2013 11:17:11 +0530 From: Bharat Bhushan To: , , , , , CC: Bharat Bhushan , Bharat Bhushan Subject: [PATCH 4/4] kvm: powerpc: set cache coherency only for RAM pages Date: Fri, 26 Jul 2013 11:16:53 +0530 Message-ID: <1374817613-20169-4-git-send-email-Bharat.Bhushan@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1374817613-20169-1-git-send-email-Bharat.Bhushan@freescale.com> References: <1374817613-20169-1-git-send-email-Bharat.Bhushan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org If the page is RAM then map this as cacheable and coherent (set "M" bit) otherwise this page is treated as I/O and map this as cache inhibited and guarded (set "I + G") This helps setting proper MMU mapping for direct assigned device. NOTE: There can be devices that require cacheable mapping, which is not yet supported. Signed-off-by: Bharat Bhushan --- arch/powerpc/kvm/e500_mmu_host.c | 24 +++++++++++++++++++----- 1 files changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c index 1c6a9d7..5cbdc8f 100644 --- a/arch/powerpc/kvm/e500_mmu_host.c +++ b/arch/powerpc/kvm/e500_mmu_host.c @@ -64,13 +64,27 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode) return mas3; } -static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode) +static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn) { + u32 mas2_attr; + + mas2_attr = mas2 & MAS2_ATTRIB_MASK; + + if (kvm_is_mmio_pfn(pfn)) { + /* + * If page is not RAM then it is treated as I/O page. + * Map it with cache inhibited and guarded (set "I" + "G"). + */ + mas2_attr |= MAS2_I | MAS2_G; + return mas2_attr; + } + + /* Map RAM pages as cacheable (Not setting "I" in MAS2) */ #ifdef CONFIG_SMP - return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M; -#else - return mas2 & MAS2_ATTRIB_MASK; + /* Also map as coherent (set "M") in SMP */ + mas2_attr |= MAS2_M; #endif + return mas2_attr; } /* @@ -313,7 +327,7 @@ static void kvmppc_e500_setup_stlbe( /* Force IPROT=0 for all guest mappings. */ stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID; stlbe->mas2 = (gvaddr & MAS2_EPN) | - e500_shadow_mas2_attrib(gtlbe->mas2, pr); + e500_shadow_mas2_attrib(gtlbe->mas2, pfn); stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) | e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);