From patchwork Fri Jul 26 02:41:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Po Liu X-Patchwork-Id: 262046 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from ozlabs.org (localhost [IPv6:::1]) by ozlabs.org (Postfix) with ESMTP id 3894C2C00FF for ; Fri, 26 Jul 2013 13:35:00 +1000 (EST) Received: by ozlabs.org (Postfix) id D8D2C2C00F9; Fri, 26 Jul 2013 13:34:33 +1000 (EST) Delivered-To: linuxppc-dev@ozlabs.org Received: from db8outboundpool.messaging.microsoft.com (mail-db8lp0186.outbound.messaging.microsoft.com [213.199.154.186]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (Client CN "mail.global.frontbridge.com", Issuer "MSIT Machine Auth CA 2" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 3AB162C00E6 for ; Fri, 26 Jul 2013 13:34:31 +1000 (EST) Received: from mail48-db8-R.bigfish.com (10.174.8.253) by DB8EHSOBE002.bigfish.com (10.174.4.65) with Microsoft SMTP Server id 14.1.225.22; Fri, 26 Jul 2013 03:34:27 +0000 Received: from mail48-db8 (localhost [127.0.0.1]) by mail48-db8-R.bigfish.com (Postfix) with ESMTP id CCF52A00283; Fri, 26 Jul 2013 03:34:27 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz1de098h1de097h8275bhz2dh2a8h668h839he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h16a6h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1de2h1dfeh1dffh1e23h1155h) Received: from mail48-db8 (localhost.localdomain [127.0.0.1]) by mail48-db8 (MessageSwitch) id 1374809639766328_12366; Fri, 26 Jul 2013 03:33:59 +0000 (UTC) Received: from DB8EHSMHS029.bigfish.com (unknown [10.174.8.249]) by mail48-db8.bigfish.com (Postfix) with ESMTP id AC13D340031; Fri, 26 Jul 2013 03:33:59 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS029.bigfish.com (10.174.4.39) with Microsoft SMTP Server (TLS) id 14.16.227.3; Fri, 26 Jul 2013 03:33:59 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.136.1; Fri, 26 Jul 2013 03:33:58 +0000 Received: from localhost (rock.ap.freescale.net [10.193.20.106]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r6Q3XuJO015153; Thu, 25 Jul 2013 20:33:56 -0700 From: Po Liu To: Subject: [PATCH v2 3/3] powerpc/85xx: Add C293PCIE board support Date: Fri, 26 Jul 2013 10:41:19 +0800 Message-ID: <1374806479-812-3-git-send-email-Po.Liu@freescale.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1374806479-812-1-git-send-email-Po.Liu@freescale.com> References: <1366854857-22791-4-git-send-email-Po.Liu@freescale.com> <1374806479-812-1-git-send-email-Po.Liu@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Cc: scottwood@freescale.com, Mingkai Hu , afleming@freescale.com, Po Liu X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" From: Mingkai Hu C293PCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu Signed-off-by: Po Liu --- Changes for v2: - Remove the JFFS2 partitions in NOR/NAND/SPI flash; - Implement the NAND partitions; - Remove the no use descriptions for cpld node; - Add mpc85xx_smp_defconfig and mpc85xx_defconfig for C293; - Remove the no use includes in c293pcie.c arch/powerpc/boot/dts/c293pcie.dts | 243 +++++++++++++++++++++++++++++ arch/powerpc/configs/mpc85xx_defconfig | 1 + arch/powerpc/configs/mpc85xx_smp_defconfig | 1 + arch/powerpc/platforms/85xx/Kconfig | 6 + arch/powerpc/platforms/85xx/Makefile | 1 + arch/powerpc/platforms/85xx/c293pcie.c | 75 +++++++++ 6 files changed, 327 insertions(+) create mode 100644 arch/powerpc/boot/dts/c293pcie.dts create mode 100644 arch/powerpc/platforms/85xx/c293pcie.c diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts new file mode 100644 index 0000000..dc91c47 --- /dev/null +++ b/arch/powerpc/boot/dts/c293pcie.dts @@ -0,0 +1,243 @@ +/* + * C293 PCIE Device Tree Source + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Freescale Semiconductor nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/include/ "fsl/c293si-pre.dtsi" + +/ { + model = "fsl,C293PCIE"; + compatible = "fsl,C293PCIE"; + + memory { + device_type = "memory"; + }; + + ifc: ifc@fffe1e000 { + reg = <0xf 0xffe1e000 0 0x2000>; + ranges = <0x0 0x0 0xf 0xec000000 0x04000000 + 0x2 0x0 0xf 0xffdf0000 0x00010000>; + + }; + + soc: soc@fffe00000 { + ranges = <0x0 0xf 0xffe00000 0x100000>; + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0 0x1000>; + ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 + 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; + pcie@0 { + ranges = <0x2000000 0x0 0x80000000 + 0x2000000 0x0 0x80000000 + 0x0 0x20000000 + + 0x1000000 0x0 0x0 + 0x1000000 0x0 0x0 + 0x0 0x100000>; + }; + }; +}; + +&ifc { + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + /* 1MB for DTB Image */ + reg = <0x0 0x00100000>; + label = "NOR DTB Image"; + }; + + partition@100000 { + /* 8 MB for Linux Kernel Image */ + reg = <0x00100000 0x00800000>; + label = "NOR Linux Kernel Image"; + }; + + partition@900000 { + /* 53MB for rootfs */ + reg = <0x00900000 0x03500000>; + label = "NOR Rootfs Image"; + }; + + partition@3e00000 { + /* 1MB for blob encrypted key */ + reg = <0x03e00000 0x00100000>; + label = "NOR blob encrypted key"; + }; + + partition@3f00000 { + /* 512KB for u-boot Bootloader Image and evn */ + reg = <0x03f00000 0x00100000>; + label = "NOR U-Boot Image"; + read-only; + }; + }; + + nand@1,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ifc-nand"; + reg = <0x1 0x0 0x10000>; + + partition@0 { + /* This location must not be altered */ + /* 1MB for u-boot Bootloader Image */ + reg = <0x0 0x00100000>; + label = "NAND U-Boot Image"; + read-only; + }; + + partition@100000 { + /* 1MB for DTB Image */ + reg = <0x00100000 0x00100000>; + label = "NAND DTB Image"; + }; + + partition@200000 { + /* 4MB for Linux Kernel Image */ + reg = <0x00200000 0x00400000>; + label = "NAND Linux Kernel Image"; + }; + + partition@600000 { + /* 19MB for Compressed Root file System Image */ + reg = <0x00600000 0x01300000>; + label = "NAND Compressed RFS Image"; + }; + + partition@1900000 { + /* 7MB for User Area */ + reg = <0x01900000 0x00700000>; + label = "NAND User area"; + }; + + partition@2000000 { + /* 96MB for Root File System */ + reg = <0x02000000 0x06000000>; + label = "NAND Root File System"; + }; + + partition@8000000 { + /* 3968MB for Others */ + reg = <0x08000000 0xF8000000>; + label = "NAND Others"; + }; + }; + + cpld@2,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,c293pcie-cpld"; + reg = <0x2 0x0 0x20>; + }; +}; + +&soc { + i2c@3000 { + eeprom@50 { + compatible = "st,24c1024"; + reg = <0x50>; + }; + + adt7461@4c { + compatible = "adi,adt7461"; + reg = <0x4c>; + }; + }; + + spi@7000 { + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25sl12801"; + reg = <0>; + spi-max-frequency = <50000000>; + + partition@0 { + /* 1MB for u-boot Bootloader Image */ + /* 1MB for Environment */ + reg = <0x0 0x00100000>; + label = "SPI Flash U-Boot Image"; + read-only; + }; + + partition@100000 { + /* 512KB for DTB Image */ + reg = <0x00100000 0x00080000>; + label = "SPI Flash DTB Image"; + }; + + partition@180000 { + /* 4MB for Linux Kernel Image */ + reg = <0x00180000 0x00400000>; + label = "SPI Flash Linux Kernel Image"; + }; + + partition@580000 { + /* 10.5MB for Compressed RFS Image */ + reg = <0x00580000 0x00a80000>; + label = "SPI Flash Compressed RFSImage"; + }; + }; + }; + + mdio@24000 { + phy0: ethernet-phy@0 { + interrupts = <2 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x2>; + }; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; +/include/ "fsl/c293si-post.dtsi" diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig index 5a58882..1592f8c 100644 --- a/arch/powerpc/configs/mpc85xx_defconfig +++ b/arch/powerpc/configs/mpc85xx_defconfig @@ -27,6 +27,7 @@ CONFIG_MPC85xx_MDS=y CONFIG_MPC8536_DS=y CONFIG_MPC85xx_DS=y CONFIG_MPC85xx_RDB=y +CONFIG_C293_PCIE=y CONFIG_P1010_RDB=y CONFIG_P1022_DS=y CONFIG_P1022_RDK=y diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig index 152fa05..d6549ff 100644 --- a/arch/powerpc/configs/mpc85xx_smp_defconfig +++ b/arch/powerpc/configs/mpc85xx_smp_defconfig @@ -30,6 +30,7 @@ CONFIG_MPC85xx_MDS=y CONFIG_MPC8536_DS=y CONFIG_MPC85xx_DS=y CONFIG_MPC85xx_RDB=y +CONFIG_C293_PCIE=y CONFIG_P1010_RDB=y CONFIG_P1022_DS=y CONFIG_P1022_RDK=y diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index efdd37c..42fc72a 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig @@ -32,6 +32,12 @@ config BSC9131_RDB StarCore SC3850 DSP Manufacturer : Freescale Semiconductor, Inc +config C293_PCIE + bool "Freescale C293PCIE" + select DEFAULT_UIMAGE + help + This option enables support for the C293PCIE board + config MPC8540_ADS bool "Freescale MPC8540 ADS" select DEFAULT_UIMAGE diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 2eab37e..53c9f75 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_SMP) += smp.o obj-y += common.o obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o +obj-$(CONFIG_C293_PCIE) += c293pcie.o obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o diff --git a/arch/powerpc/platforms/85xx/c293pcie.c b/arch/powerpc/platforms/85xx/c293pcie.c new file mode 100644 index 0000000..6208e49 --- /dev/null +++ b/arch/powerpc/platforms/85xx/c293pcie.c @@ -0,0 +1,75 @@ +/* + * C293PCIE Board Setup + * + * Copyright 2013 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "mpc85xx.h" + +void __init c293_pcie_pic_init(void) +{ + struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | + MPIC_SINGLE_DEST_CPU, 0, 256, " OpenPIC "); + + BUG_ON(mpic == NULL); + + mpic_init(mpic); +} + + +/* + * Setup the architecture + */ +static void __init c293_pcie_setup_arch(void) +{ + if (ppc_md.progress) + ppc_md.progress("c293_pcie_setup_arch()", 0); + + fsl_pci_assign_primary(); + + printk(KERN_INFO "C293 PCIE board from Freescale Semiconductor\n"); +} + +machine_arch_initcall(c293_pcie, mpc85xx_common_publish_devices); + +/* + * Called very early, device-tree isn't unflattened + */ +static int __init c293_pcie_probe(void) +{ + unsigned long root = of_get_flat_dt_root(); + + if (of_flat_dt_is_compatible(root, "fsl,C293PCIE")) + return 1; + return 0; +} + +define_machine(c293_pcie) { + .name = "C293 PCIE", + .probe = c293_pcie_probe, + .setup_arch = c293_pcie_setup_arch, + .init_IRQ = c293_pcie_pic_init, +#ifdef CONFIG_PCI + .pcibios_fixup_bus = fsl_pcibios_fixup_bus, +#endif + .get_irq = mpic_get_irq, + .restart = fsl_rstcr_restart, + .calibrate_decr = generic_calibrate_decr, + .progress = udbg_progress, +};