From patchwork Thu Jul 25 17:53:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 261836 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B6CD22C0097 for ; Fri, 26 Jul 2013 03:56:41 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757386Ab3GYRzG (ORCPT ); Thu, 25 Jul 2013 13:55:06 -0400 Received: from mail-bk0-f54.google.com ([209.85.214.54]:40188 "EHLO mail-bk0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932103Ab3GYRzB (ORCPT ); Thu, 25 Jul 2013 13:55:01 -0400 Received: by mail-bk0-f54.google.com with SMTP id it19so806945bkc.27 for ; Thu, 25 Jul 2013 10:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=gIUYPsllVoWyX4J3I1/PSAC3KNWvUJQJtxgB8t7+4qU=; b=N73lFTBzuU0gJr5sEMv/uj79Vo0j4qh0YcKbfe+Q4FBFAFZuWlRjAxElabKa6HPqLF Yzex4P3E66y77+NHAhfM6PLB3lzFYReBjZgwzjFpQPbe1N4ReQv+lQ5AIerRaFCqD5la 8BARABALTrbVsBuiwPJuW6kg1q/9U/D5ZTivuc1RRIK2pwIwum6Ex6npMDpTpP8YteZk XbmNieYcEjZkx+pZ4zPrjDL4I3YVNBV+GpihRuPJWu4+Ix8UwnrEyCOuszo/HvKHYFFJ rQa+X9s10xfbhBoO5tCwu2ZW7PSsBL+v0A1fW7PmTHRXYGUPCA/mScX+4Yw7WGwGhF+D sDpg== X-Received: by 10.204.117.1 with SMTP id o1mr6625313bkq.103.1374774899539; Thu, 25 Jul 2013 10:54:59 -0700 (PDT) Received: from localhost (dotsec.net. [62.75.224.215]) by mx.google.com with ESMTPSA id fc7sm11355285bkc.3.2013.07.25.10.54.55 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 10:54:58 -0700 (PDT) From: Thierry Reding To: Bjorn Helgaas , Stephen Warren Cc: Russell King , Jason Cooper , Thomas Petazzoni , Jay Agarwal , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 13/16] ARM: tegra: Fix Beaver's PCIe lane configuration Date: Thu, 25 Jul 2013 10:53:27 -0700 Message-Id: <1374774810-18459-14-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> References: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Stephen Warren Beaver's PCIe lane configuration most closely matches x2 x2 x2 rather than x4 x1 x1, since clocks 0 and 2 are used, and lanes 0 and 5 are used, and the only way those align is with a x2 x2 x2 configuration. Also, disable root port 1; there's nothing connected to it. Root port 0 is the on-board PCIe Ethernet, and port 2 is the mini-PCIe slot. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra30-beaver.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 4d9fa31..e1dd644 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -18,16 +18,16 @@ pci@1,0 { status = "okay"; - nvidia,num-lanes = <4>; + nvidia,num-lanes = <2>; }; pci@2,0 { - status = "okay"; - nvidia,num-lanes = <1>; + nvidia,num-lanes = <2>; }; pci@3,0 { - nvidia,num-lanes = <1>; + status = "okay"; + nvidia,num-lanes = <2>; }; };