From patchwork Thu Jul 25 17:53:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 261831 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4DDD52C00DD for ; Fri, 26 Jul 2013 03:56:28 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757574Ab3GYRzZ (ORCPT ); Thu, 25 Jul 2013 13:55:25 -0400 Received: from mail-bk0-f51.google.com ([209.85.214.51]:33292 "EHLO mail-bk0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932145Ab3GYRzO (ORCPT ); Thu, 25 Jul 2013 13:55:14 -0400 Received: by mail-bk0-f51.google.com with SMTP id ji1so815686bkc.10 for ; Thu, 25 Jul 2013 10:55:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=IRD8AVa0tUQILc+6sc6eXT4SMN1gHsauBiDLDX8lQXU=; b=ahjfN+OdUBMj2/+idHKECat3+FLMkRdyGx6/NYhjhV/wBHowf/XpR/4yUCaiF9pWPE OlPHkNRAxde+h2JSZe34GSuND+LlFbi0h5OsMwN3xtRyygWBMzYeseksUUFGrvdhptky vCoTwjj9Y0yENHJXMVdwwoMY/K8+a4S6baoUB0MPHGp8N0mLiO5mQNIR2XyXunzRn1Ct 2qeYYh/5e+U3YHpcgc0L4tTHjKfHH9kL6X/Drxc19P+K4b18EkhHw5Z9ucUO8ehzpNe7 Jz4DAgrbZd2ppwjdIo1Q12Q+UrDg8ewlhyqA5RGTRKdHUo1T0yuDmbpOvFjHSLxIJ3Vt 9j1w== X-Received: by 10.205.5.6 with SMTP id oe6mr2210536bkb.36.1374774912024; Thu, 25 Jul 2013 10:55:12 -0700 (PDT) Received: from localhost (dotsec.net. [62.75.224.215]) by mx.google.com with ESMTPSA id fc7sm11355474bkc.3.2013.07.25.10.55.08 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 10:55:11 -0700 (PDT) From: Thierry Reding To: Bjorn Helgaas , Stephen Warren Cc: Russell King , Jason Cooper , Thomas Petazzoni , Jay Agarwal , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 15/16] ARM: dts: tegra: Increase prefetchable PCI memory space Date: Thu, 25 Jul 2013 10:53:29 -0700 Message-Id: <1374774810-18459-16-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> References: <1374774810-18459-1-git-send-email-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Jay Agarwal Instead of evenly splitting the 512 MiB area between prefetchable and non-prefetchable memory spaces, increase the prefetchable memory space to 384 MiB while at the same time decreasing the non-prefetchable memory space to 128 MiB. This is a more useful default as most PCIe devices require more prefetchable than non-prefetchable memory. Signed-off-by: Jay Agarwal Tested-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20.dtsi | 4 ++-- arch/arm/boot/dts/tegra30.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index ecd016a..3add9ac2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -473,8 +473,8 @@ ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */ 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */ 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */ - 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */ + 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>, diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index c8facca..d81c52e 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -35,8 +35,8 @@ 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ - 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ + 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ + 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>,