Patchwork [U-Boot,v4,1/2] mx6: Factor out common HDMI setup code

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Submitter Pardeep Kumar Singla
Date July 25, 2013, 5:12 p.m.
Message ID <1374772334-2410-1-git-send-email-b45784@freescale.com>
Download mbox | patch
Permalink /patch/261799/
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Comments

Pardeep Kumar Singla - July 25, 2013, 5:12 p.m.
Instead of duplicating HDMI setup code for every mx6 board, factor out the common code

Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
---
Changes since v3:
Added declaration of enable_ipu_clock(). 
Made enable_ipu_clock() function public.

 arch/arm/cpu/armv7/mx6/clock.c                |    8 +++++
 arch/arm/cpu/armv7/mx6/soc.c                  |   43 +++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h         |    2 +-
 arch/arm/include/asm/arch-mx6/mxc_hdmi.h      |    5 +++
 board/boundary/nitrogen6x/nitrogen6x.c        |   44 ++++-------------------
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   46 +++++--------------------
 board/wandboard/wandboard.c                   |   44 +++--------------------
 include/configs/mx6qsabrelite.h               |    1 +
 include/configs/nitrogen6x.h                  |    1 +
 include/configs/wandboard.h                   |    1 +
 10 files changed, 79 insertions(+), 116 deletions(-)
Eric Nelson - July 25, 2013, 5:28 p.m.
On 07/25/2013 10:12 AM, Pardeep Kumar Singla wrote:
> Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
>
> Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
> ---
> Changes since v3:
> Added declaration of enable_ipu_clock().
> Made enable_ipu_clock() function public.
>
>   arch/arm/cpu/armv7/mx6/clock.c                |    8 +++++
>   arch/arm/cpu/armv7/mx6/soc.c                  |   43 +++++++++++++++++++++++
>   arch/arm/include/asm/arch-mx6/clock.h         |    2 +-
>   arch/arm/include/asm/arch-mx6/mxc_hdmi.h      |    5 +++
>   board/boundary/nitrogen6x/nitrogen6x.c        |   44 ++++-------------------
>   board/freescale/mx6qsabrelite/mx6qsabrelite.c |   46 +++++--------------------
>   board/wandboard/wandboard.c                   |   44 +++--------------------
>   include/configs/mx6qsabrelite.h               |    1 +
>   include/configs/nitrogen6x.h                  |    1 +
>   include/configs/wandboard.h                   |    1 +
>   10 files changed, 79 insertions(+), 116 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index 3c0d908..a724e66 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -468,6 +468,14 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>   	return 0;
>   }
>
> +void enable_ipu_clock()
> +{
> +	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	int reg;
> +	reg = readl(&mxc_ccm->CCGR3);
> +	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
> +	writel(reg, &mxc_ccm->CCGR3);
> +}
>   /***************************************************/
>
>   U_BOOT_CMD(
> diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
> index fc436fb..a79369f 100644
> --- a/arch/arm/cpu/armv7/mx6/soc.c
> +++ b/arch/arm/cpu/armv7/mx6/soc.c
> @@ -32,6 +32,8 @@
>   #include <asm/imx-common/boot_mode.h>
>   #include <asm/imx-common/dma.h>
>   #include <stdbool.h>
> +#include <asm/arch/mxc_hdmi.h>
> +#include <asm/arch/crm_regs.h>
>
>   struct scu_regs {
>   	u32	ctrl;
> @@ -228,3 +230,44 @@ const struct boot_mode soc_boot_modes[] = {
>   void s_init(void)
>   {
>   }
> +
> +#ifdef CONFIG_IMX_HDMI
> +void imx_enable_hdmi_phy(void)
> +{
> +	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> +	u8 reg;
> +	reg = readb(&hdmi->phy_conf0);
> +	reg |= HDMI_PHY_CONF0_PDZ_MASK;
> +	writeb(reg, &hdmi->phy_conf0);
> +	udelay(3000);
> +	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
> +	writeb(reg, &hdmi->phy_conf0);
> +	udelay(3000);
> +	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
> +	writeb(reg, &hdmi->phy_conf0);
> +	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
> +}
> +
> +void imx_setup_hdmi(void)
> +{
> +	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> +	int reg;
> +
> +	/* Turn on HDMI PHY clock */
> +	reg = readl(&mxc_ccm->CCGR2);
> +	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
> +		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
> +	writel(reg, &mxc_ccm->CCGR2);
> +	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
> +	reg = readl(&mxc_ccm->chsccdr);
> +	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
> +		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
> +		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
> +	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
> +		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
> +		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
> +		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
> +	writel(reg, &mxc_ccm->chsccdr);
> +}
> +#endif
> diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
> index cfd4edc..d9f7fc5 100644
> --- a/arch/arm/include/asm/arch-mx6/clock.h
> +++ b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -65,5 +65,5 @@ void enable_ocotp_clk(unsigned char enable);
>   void enable_usboh3_clk(unsigned char enable);
>   int enable_sata_clock(void);
>   int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
> -
> +void enable_ipu_clock();
>   #endif /* __ASM_ARCH_CLOCK_H */
> diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
> index 9dccb3f..5cd6aa6 100644
> --- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
> +++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
> @@ -21,6 +21,11 @@
>   #ifndef __MXC_HDMI_H__
>   #define __MXC_HDMI_H__
>
> +#ifdef CONFIG_IMX_HDMI
> +void imx_enable_hdmi_phy(void);
> +void imx_setup_hdmi(void);
> +#endif
> +
>   /*
>    * Hdmi controller registers
>    */
> diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
> index 8f0f9b8..1b82633 100644
> --- a/board/boundary/nitrogen6x/nitrogen6x.c
> +++ b/board/boundary/nitrogen6x/nitrogen6x.c
> @@ -480,22 +480,9 @@ static int detect_hdmi(struct display_info_t const *dev)
>   	return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
>   }
>
> -static void enable_hdmi(struct display_info_t const *dev)
> +static void do_enable_hdmi(struct display_info_t const *dev)
>   {
> -	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> -	u8 reg;
> -	printf("%s: setup HDMI monitor\n", __func__);
> -	reg = readb(&hdmi->phy_conf0);
> -	reg |= HDMI_PHY_CONF0_PDZ_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -
> -	udelay(3000);
> -	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -	udelay(3000);
> -	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
> +	imx_enable_hdmi_phy();
>   }
>
>   static int detect_i2c(struct display_info_t const *dev)
> @@ -528,7 +515,7 @@ static struct display_info_t const displays[] = {{
>   	.addr	= 0,
>   	.pixfmt	= IPU_PIX_FMT_RGB24,
>   	.detect	= detect_hdmi,
> -	.enable	= enable_hdmi,
> +	.enable	= do_enable_hdmi,
>   	.mode	= {
>   		.name           = "HDMI",
>   		.refresh        = 60,
> @@ -653,25 +640,15 @@ static void setup_display(void)
>   	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>   	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
>   	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> -	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> -
>   	int reg;
>
> +	enable_ipu_clock();
> +	imx_setup_hdmi();
>   	/* Turn on LDB0,IPU,IPU DI0 clocks */
>   	reg = __raw_readl(&mxc_ccm->CCGR3);
> -	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
> -		|MXC_CCM_CCGR3_LDB_DI0_MASK;
> +	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
>   	writel(reg, &mxc_ccm->CCGR3);
>
> -	/* Turn on HDMI PHY clock */
> -	reg = __raw_readl(&mxc_ccm->CCGR2);
> -	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
> -	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
> -	writel(reg, &mxc_ccm->CCGR2);
> -
> -	/* clear HDMI PHY reset */
> -	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
> -
>   	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
>   	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
>   	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
> @@ -689,15 +666,8 @@ static void setup_display(void)
>   	writel(reg, &mxc_ccm->cscmr2);
>
>   	reg = readl(&mxc_ccm->chsccdr);
> -	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
> -		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
> -		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
>   	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> -		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
> -	      |(CHSCCDR_PODF_DIVIDE_BY_3
> -		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
> -	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
> -		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
> +		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
>   	writel(reg, &mxc_ccm->chsccdr);
>
>   	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
> diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> index 862bc30..3ac4f71 100644
> --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
> @@ -452,24 +452,10 @@ static int detect_hdmi(struct display_info_t const *dev)
>   	return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
>   }
>
> -static void enable_hdmi(struct display_info_t const *dev)
> +static void do_enable_hdmi(struct display_info_t const *dev)
>   {
> -	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> -	u8 reg;
> -	printf("%s: setup HDMI monitor\n", __func__);
> -	reg = readb(&hdmi->phy_conf0);
> -	reg |= HDMI_PHY_CONF0_PDZ_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -
> -	udelay(3000);
> -	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -	udelay(3000);
> -	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
> +	 imx_enable_hdmi_phy();
>   }
> -
>   static int detect_i2c(struct display_info_t const *dev)
>   {
>   	return ((0 == i2c_set_bus_num(dev->bus))
> @@ -500,7 +486,7 @@ static struct display_info_t const displays[] = {{
>   	.addr	= 0,
>   	.pixfmt	= IPU_PIX_FMT_RGB24,
>   	.detect	= detect_hdmi,
> -	.enable	= enable_hdmi,
> +	.enable	= do_enable_hdmi,
>   	.mode	= {
>   		.name           = "HDMI",
>   		.refresh        = 60,
> @@ -625,25 +611,16 @@ static void setup_display(void)
>   	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>   	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
>   	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
> -	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> -
>   	int reg;
>
> +	enable_ipu_clock();
> +	imx_setup_hdmi();
> +
>   	/* Turn on LDB0,IPU,IPU DI0 clocks */
>   	reg = __raw_readl(&mxc_ccm->CCGR3);
> -	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
> -		|MXC_CCM_CCGR3_LDB_DI0_MASK;
> +	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
>   	writel(reg, &mxc_ccm->CCGR3);
>
> -	/* Turn on HDMI PHY clock */
> -	reg = __raw_readl(&mxc_ccm->CCGR2);
> -	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
> -	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
> -	writel(reg, &mxc_ccm->CCGR2);
> -
> -	/* clear HDMI PHY reset */
> -	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
> -
>   	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
>   	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
>   	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
> @@ -661,15 +638,8 @@ static void setup_display(void)
>   	writel(reg, &mxc_ccm->cscmr2);
>
>   	reg = readl(&mxc_ccm->chsccdr);
> -	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
> -		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
> -		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
>   	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> -		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
> -	      |(CHSCCDR_PODF_DIVIDE_BY_3
> -		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
> -	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
> -		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
> +		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
>   	writel(reg, &mxc_ccm->chsccdr);
>
>   	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
> diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
> index 43c02ac..6cd28ed 100644
> --- a/board/wandboard/wandboard.c
> +++ b/board/wandboard/wandboard.c
> @@ -211,23 +211,6 @@ int board_phy_config(struct phy_device *phydev)
>   }
>
>   #if defined(CONFIG_VIDEO_IPUV3)
> -static void enable_hdmi(void)
> -{
> -	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
> -	u8 reg;
> -	reg = readb(&hdmi->phy_conf0);
> -	reg |= HDMI_PHY_CONF0_PDZ_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -
> -	udelay(3000);
> -	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -	udelay(3000);
> -	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
> -	writeb(reg, &hdmi->phy_conf0);
> -	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
> -}
> -
>   static struct fb_videomode const hdmi = {
>   	.name           = "HDMI",
>   	.refresh        = 60,
> @@ -253,7 +236,7 @@ int board_video_skip(void)
>   	if (ret)
>   		printf("HDMI cannot be configured: %d\n", ret);
>
> -	enable_hdmi();
> +	imx_enable_hdmi_phy();
>
>   	return ret;
>   }
> @@ -261,33 +244,14 @@ int board_video_skip(void)
>   static void setup_display(void)
>   {
>   	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> -	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
>   	int reg;
>
> -	/* Turn on IPU clock */
> -	reg = readl(&mxc_ccm->CCGR3);
> -	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
> -	writel(reg, &mxc_ccm->CCGR3);
> -
> -	/* Turn on HDMI PHY clock */
> -	reg = readl(&mxc_ccm->CCGR2);
> -	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
> -		| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
> -	writel(reg, &mxc_ccm->CCGR2);
> -
> -	/* clear HDMI PHY reset */
> -	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
> +	enable_ipu_clock();
> +	imx_setup_hdmi();
>
>   	reg = readl(&mxc_ccm->chsccdr);
> -	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
> -		| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
> -		| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
>   	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
> -		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
> -	      | (CHSCCDR_PODF_DIVIDE_BY_3
> -		<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
> -	      | (CHSCCDR_IPU_PRE_CLK_540M_PFD
> -		<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
> +		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
>   	writel(reg, &mxc_ccm->chsccdr);
>   }
>   #endif /* CONFIG_VIDEO_IPUV3 */
> diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
> index c7db81d..6127347 100644
> --- a/include/configs/mx6qsabrelite.h
> +++ b/include/configs/mx6qsabrelite.h
> @@ -141,6 +141,7 @@
>   #define CONFIG_BMP_16BPP
>   #define CONFIG_VIDEO_LOGO
>   #define CONFIG_IPUV3_CLK 260000000
> +#define CONFIG_IMX_HDMI
>
>   /* allow to overwrite serial and ethaddr */
>   #define CONFIG_ENV_OVERWRITE
> diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
> index 74df66c..0b665dc 100644
> --- a/include/configs/nitrogen6x.h
> +++ b/include/configs/nitrogen6x.h
> @@ -154,6 +154,7 @@
>   #define CONFIG_IPUV3_CLK 260000000
>   #define CONFIG_CMD_HDMIDETECT
>   #define CONFIG_CONSOLE_MUX
> +#define CONFIG_IMX_HDMI
>
>   /* allow to overwrite serial and ethaddr */
>   #define CONFIG_ENV_OVERWRITE
> diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
> index dd06bd7..1f83e89 100644
> --- a/include/configs/wandboard.h
> +++ b/include/configs/wandboard.h
> @@ -100,6 +100,7 @@
>   #define CONFIG_VIDEO_LOGO
>   #define CONFIG_VIDEO_BMP_LOGO
>   #define CONFIG_IPUV3_CLK 260000000
> +#define CONFIG_IMX_HDMI
>
>   #if defined(CONFIG_MX6DL)
>   #define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"
>

Acked-By: Eric Nelson <eric.nelson@boundarydevices.com>
Stefano Babic - July 27, 2013, 8:46 a.m.
Hi Pardeep,

On 25/07/2013 19:12, Pardeep Kumar Singla wrote:
> -
> +void enable_ipu_clock();

This generates a warning:

 warning: function declaration isn't a prototype [-Wstrict-prototypes]

I fix it myself.

Best regards,
Stefano Babic
Stefano Babic - July 27, 2013, 8:55 a.m.
On 25/07/2013 19:12, Pardeep Kumar Singla wrote:
> Instead of duplicating HDMI setup code for every mx6 board, factor out the common code
> 
> Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com>
> ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Patch

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 3c0d908..a724e66 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -468,6 +468,14 @@  int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+void enable_ipu_clock()
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int reg;
+	reg = readl(&mxc_ccm->CCGR3);
+	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+	writel(reg, &mxc_ccm->CCGR3);
+}
 /***************************************************/
 
 U_BOOT_CMD(
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index fc436fb..a79369f 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -32,6 +32,8 @@ 
 #include <asm/imx-common/boot_mode.h>
 #include <asm/imx-common/dma.h>
 #include <stdbool.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
 
 struct scu_regs {
 	u32	ctrl;
@@ -228,3 +230,44 @@  const struct boot_mode soc_boot_modes[] = {
 void s_init(void)
 {
 }
+
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void)
+{
+	struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	u8 reg;
+	reg = readb(&hdmi->phy_conf0);
+	reg |= HDMI_PHY_CONF0_PDZ_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	udelay(3000);
+	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+	writeb(reg, &hdmi->phy_conf0);
+	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+}
+
+void imx_setup_hdmi(void)
+{
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+	int reg;
+
+	/* Turn on HDMI PHY clock */
+	reg = readl(&mxc_ccm->CCGR2);
+	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+		 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+	writel(reg, &mxc_ccm->CCGR2);
+	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+	reg = readl(&mxc_ccm->chsccdr);
+	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+		 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+	reg |= (CHSCCDR_PODF_DIVIDE_BY_3
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+		 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
+		 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+	writel(reg, &mxc_ccm->chsccdr);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index cfd4edc..d9f7fc5 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -65,5 +65,5 @@  void enable_ocotp_clk(unsigned char enable);
 void enable_usboh3_clk(unsigned char enable);
 int enable_sata_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
-
+void enable_ipu_clock();
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
index 9dccb3f..5cd6aa6 100644
--- a/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
+++ b/arch/arm/include/asm/arch-mx6/mxc_hdmi.h
@@ -21,6 +21,11 @@ 
 #ifndef __MXC_HDMI_H__
 #define __MXC_HDMI_H__
 
+#ifdef CONFIG_IMX_HDMI
+void imx_enable_hdmi_phy(void);
+void imx_setup_hdmi(void);
+#endif
+
 /*
  * Hdmi controller registers
  */
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 8f0f9b8..1b82633 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -480,22 +480,9 @@  static int detect_hdmi(struct display_info_t const *dev)
 	return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 }
 
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
 {
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	u8 reg;
-	printf("%s: setup HDMI monitor\n", __func__);
-	reg = readb(&hdmi->phy_conf0);
-	reg |= HDMI_PHY_CONF0_PDZ_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+	imx_enable_hdmi_phy();
 }
 
 static int detect_i2c(struct display_info_t const *dev)
@@ -528,7 +515,7 @@  static struct display_info_t const displays[] = {{
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
 	.detect	= detect_hdmi,
-	.enable	= enable_hdmi,
+	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
 		.refresh        = 60,
@@ -653,25 +640,15 @@  static void setup_display(void)
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
 	int reg;
 
+	enable_ipu_clock();
+	imx_setup_hdmi();
 	/* Turn on LDB0,IPU,IPU DI0 clocks */
 	reg = __raw_readl(&mxc_ccm->CCGR3);
-	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
-		|MXC_CCM_CCGR3_LDB_DI0_MASK;
+	reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 
-	/* Turn on HDMI PHY clock */
-	reg = __raw_readl(&mxc_ccm->CCGR2);
-	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-	writel(reg, &mxc_ccm->CCGR2);
-
-	/* clear HDMI PHY reset */
-	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
 	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@@ -689,15 +666,8 @@  static void setup_display(void)
 	writel(reg, &mxc_ccm->cscmr2);
 
 	reg = readl(&mxc_ccm->chsccdr);
-	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-	      |(CHSCCDR_PODF_DIVIDE_BY_3
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
 
 	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 862bc30..3ac4f71 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -452,24 +452,10 @@  static int detect_hdmi(struct display_info_t const *dev)
 	return readb(&hdmi->phy_stat0) & HDMI_PHY_HPD;
 }
 
-static void enable_hdmi(struct display_info_t const *dev)
+static void do_enable_hdmi(struct display_info_t const *dev)
 {
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	u8 reg;
-	printf("%s: setup HDMI monitor\n", __func__);
-	reg = readb(&hdmi->phy_conf0);
-	reg |= HDMI_PHY_CONF0_PDZ_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
+	 imx_enable_hdmi_phy();
 }
-
 static int detect_i2c(struct display_info_t const *dev)
 {
 	return ((0 == i2c_set_bus_num(dev->bus))
@@ -500,7 +486,7 @@  static struct display_info_t const displays[] = {{
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
 	.detect	= detect_hdmi,
-	.enable	= enable_hdmi,
+	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
 		.refresh        = 60,
@@ -625,25 +611,16 @@  static void setup_display(void)
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-
 	int reg;
 
+	enable_ipu_clock();
+	imx_setup_hdmi();
+
 	/* Turn on LDB0,IPU,IPU DI0 clocks */
 	reg = __raw_readl(&mxc_ccm->CCGR3);
-	reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
-		|MXC_CCM_CCGR3_LDB_DI0_MASK;
+	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 	writel(reg, &mxc_ccm->CCGR3);
 
-	/* Turn on HDMI PHY clock */
-	reg = __raw_readl(&mxc_ccm->CCGR2);
-	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-	       |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-	writel(reg, &mxc_ccm->CCGR2);
-
-	/* clear HDMI PHY reset */
-	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
-
 	/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 	writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 	writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
@@ -661,15 +638,8 @@  static void setup_display(void)
 	writel(reg, &mxc_ccm->cscmr2);
 
 	reg = readl(&mxc_ccm->chsccdr);
-	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-		|MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-	      |(CHSCCDR_PODF_DIVIDE_BY_3
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-	      |(CHSCCDR_IPU_PRE_CLK_540M_PFD
-		<<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
 
 	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 43c02ac..6cd28ed 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -211,23 +211,6 @@  int board_phy_config(struct phy_device *phydev)
 }
 
 #if defined(CONFIG_VIDEO_IPUV3)
-static void enable_hdmi(void)
-{
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
-	u8 reg;
-	reg = readb(&hdmi->phy_conf0);
-	reg |= HDMI_PHY_CONF0_PDZ_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	udelay(3000);
-	reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
-	writeb(reg, &hdmi->phy_conf0);
-	writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
-}
-
 static struct fb_videomode const hdmi = {
 	.name           = "HDMI",
 	.refresh        = 60,
@@ -253,7 +236,7 @@  int board_video_skip(void)
 	if (ret)
 		printf("HDMI cannot be configured: %d\n", ret);
 
-	enable_hdmi();
+	imx_enable_hdmi_phy();
 
 	return ret;
 }
@@ -261,33 +244,14 @@  int board_video_skip(void)
 static void setup_display(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-	struct hdmi_regs *hdmi	= (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 	int reg;
 
-	/* Turn on IPU clock */
-	reg = readl(&mxc_ccm->CCGR3);
-	reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
-	writel(reg, &mxc_ccm->CCGR3);
-
-	/* Turn on HDMI PHY clock */
-	reg = readl(&mxc_ccm->CCGR2);
-	reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
-		| MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
-	writel(reg, &mxc_ccm->CCGR2);
-
-	/* clear HDMI PHY reset */
-	writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
+	enable_ipu_clock();
+	imx_setup_hdmi();
 
 	reg = readl(&mxc_ccm->chsccdr);
-	reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
-		| MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
-		| MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
-	      | (CHSCCDR_PODF_DIVIDE_BY_3
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
-	      | (CHSCCDR_IPU_PRE_CLK_540M_PFD
-		<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 	writel(reg, &mxc_ccm->chsccdr);
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
index c7db81d..6127347 100644
--- a/include/configs/mx6qsabrelite.h
+++ b/include/configs/mx6qsabrelite.h
@@ -141,6 +141,7 @@ 
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 74df66c..0b665dc 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -154,6 +154,7 @@ 
 #define CONFIG_IPUV3_CLK 260000000
 #define CONFIG_CMD_HDMIDETECT
 #define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index dd06bd7..1f83e89 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -100,6 +100,7 @@ 
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
 
 #if defined(CONFIG_MX6DL)
 #define CONFIG_DEFAULT_FDT_FILE		"imx6dl-wandboard.dtb"