Patchwork [U-Boot,1/2] fpga: zynqpl: Add support for zc7100 device.

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Submitter Michal Simek
Date July 25, 2013, 2:06 p.m.
Message ID <a764db7728c3e573ec7ea2bc36335607b5fa05d7.1374761192.git.michal.simek@xilinx.com>
Download mbox | patch
Permalink /patch/261702/
State Accepted
Delegated to: Michal Simek
Headers show

Comments

Michal Simek - July 25, 2013, 2:06 p.m.
- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 board/xilinx/zynq/board.c | 4 ++++
 drivers/fpga/zynqpl.c     | 2 +-
 include/zynqpl.h          | 5 +++++
 3 files changed, 10 insertions(+), 1 deletion(-)

--
1.8.2.3

Patch

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index b02c364..c2046cf 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -36,6 +36,7 @@  Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif

 int board_init(void)
@@ -58,6 +59,9 @@  int board_init(void)
 	case XILINX_ZYNQ_7045:
 		fpga = fpga045;
 		break;
+	case XILINX_ZYNQ_7100:
+		fpga = fpga100;
+		break;
 	}
 #endif

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 8feccde..6a5764f 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -47,7 +47,7 @@ 
 #endif

 #ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ	/* 1 s */
+#define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
 #endif

 int zynq_info(Xilinx_desc *desc)
diff --git a/include/zynqpl.h b/include/zynqpl.h
index 0247ef6..c5ea745 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -36,12 +36,14 @@  extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
 #define XILINX_ZYNQ_7045	0x11
+#define XILINX_ZYNQ_7100	0x16

 /* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE	16669920/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
 #define XILINX_XC7Z045_SIZE	106571232/8
+#define XILINX_XC7Z100_SIZE	139330784/8

 /* Descriptor Macros */
 #define XILINX_XC7Z010_DESC(cookie) \
@@ -56,4 +58,7 @@  extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_XC7Z045_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }

+#define XILINX_XC7Z100_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+
 #endif /* _ZYNQPL_H_ */