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[1.164.252.144]) by mx.google.com with ESMTPSA id y6sm49229028pbl.23.2013.07.24.11.18.04 for (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 24 Jul 2013 11:18:06 -0700 (PDT) From: Kuan-Yu Kuo To: u-boot@lists.denx.de, wd@denx.de, dzu@denx.de Date: Thu, 25 Jul 2013 02:17:11 +0800 Message-Id: <1374689831-10024-1-git-send-email-ken.kuoky@gmail.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1374081632-3684-1-git-send-email-ken.kuoky@gmail.com> References: <1374081632-3684-1-git-send-email-ken.kuoky@gmail.com> Cc: uboot@andestech.com Subject: [U-Boot] [PATCH v2] nds32: Enable FPU if the version of CPU supported X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Some version of Andes core support FPU coprocessor, if this is the case, and toolchain support FPU instruction set, we should enable it at low level initialization time. Signed-off-by: Kuan-Yu Kuo Cc: Macpaul Lin --- Change for v2: - Add compile option to determine if current used toolchain support FPU instruction or not. arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 26 ++++++++++++++++++++++++++ arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 26 ++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index 55985cf..021de86 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -98,6 +98,11 @@ lowlevel_init: led 0x10 jal remap +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + led 0x1f + jal enable_fpu +#endif + led 0x20 ret $r10 @@ -234,6 +239,27 @@ relo_base: 2: ret + /* + * enable_fpu: + * Some of Andes CPU version support FPU coprocessor, if so, + * and toolchain support FPU instruction set, we should enable it. + */ +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) +enable_fpu: + mfsr $r0, $CPU_VER /* enable FPU if it exists */ + srli $r0, $r0, 3 + andi $r0, $r0, 1 + beqz $r0, 1f /* skip if no COP */ + mfsr $r0, $FUCOP_EXIST + srli $r0, $r0, 31 + beqz $r0, 1f /* skip if no FPU */ + mfsr $r0, $FUCOP_CTL + ori $r0, $r0, 1 + mtsr $r0, $FUCOP_CTL +1: + ret +#endif + .globl show_led show_led: li $r8, (CONFIG_DEBUG_LED) diff --git a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S index d842afa..d3b9e16 100644 --- a/arch/nds32/cpu/n1213/ag102/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag102/lowlevel_init.S @@ -114,6 +114,11 @@ lowlevel_init: led 0x20 jal remap +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + led 0x2f + jal enable_fpu +#endif + led 0x30 ret $r10 @@ -289,6 +294,27 @@ relo_base: 2: ret + /* + * enable_fpu: + * Some of Andes CPU version support FPU coprocessor, if so, + * and toolchain support FPU instruction set, we should enable it. + */ +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) +enable_fpu: + mfsr $r0, $CPU_VER /* enable FPU if it exists */ + srli $r0, $r0, 3 + andi $r0, $r0, 1 + beqz $r0, 1f /* skip if no COP */ + mfsr $r0, $FUCOP_EXIST + srli $r0, $r0, 31 + beqz $r0, 1f /* skip if no FPU */ + mfsr $r0, $FUCOP_CTL + ori $r0, $r0, 1 + mtsr $r0, $FUCOP_CTL +1: + ret +#endif + .globl show_led show_led: li $r8, (CONFIG_DEBUG_LED)