From patchwork Wed Jul 24 04:09:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Zhao X-Patchwork-Id: 261273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 604882C00BB for ; Wed, 24 Jul 2013 14:13:36 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751276Ab3GXEKz (ORCPT ); Wed, 24 Jul 2013 00:10:55 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:8520 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750911Ab3GXEKP (ORCPT ); Wed, 24 Jul 2013 00:10:15 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 23 Jul 2013 21:10:07 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 23 Jul 2013 21:10:14 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 23 Jul 2013 21:10:14 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 23 Jul 2013 21:10:13 -0700 Received: from rizhao-lap.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 24 Jul 2013 12:10:08 +0800 From: Richard Zhao To: , , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH 5/9] spi: tegra20-sflash: move to generic dma DT binding Date: Wed, 24 Jul 2013 12:09:58 +0800 Message-ID: <1374639002-16753-6-git-send-email-rizhao@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1374639002-16753-1-git-send-email-rizhao@nvidia.com> References: <1374639002-16753-1-git-send-email-rizhao@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org update binding doc. Signed-off-by: Richard Zhao --- .../devicetree/bindings/spi/nvidia,tegra20-sflash.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt index 7b53da5..fa22d1b 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra20-sflash.txt @@ -4,8 +4,11 @@ Required properties: - compatible : should be "nvidia,tegra20-sflash". - reg: Should contain SFLASH registers location and length. - interrupts: Should contain SFLASH interrupts. -- nvidia,dma-request-selector : The Tegra DMA controller's phandle and - request selector for this SFLASH controller. + +Optional properties: +- dmas : The Tegra DMA controller's phandle and request selector for + this SFLASH controller. +- dma-names : Should be "rx-tx". Recommended properties: - spi-max-frequency: Definition as per @@ -17,7 +20,8 @@ spi@7000c380 { compatible = "nvidia,tegra20-sflash"; reg = <0x7000c380 0x80>; interrupts = <0 39 0x04>; - nvidia,dma-request-selector = <&apbdma 16>; + dmas = <&apbdma 16>; + dma-names = "rx-tx"; spi-max-frequency = <25000000>; #address-cells = <1>; #size-cells = <0>;