From patchwork Tue Jul 23 09:33:15 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mian M. 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[86.73.107.68]) by mx.google.com with ESMTPSA id f8sm2158705wiv.0.2013.07.23.02.33.43 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 23 Jul 2013 02:33:44 -0700 (PDT) From: "Mian M. Hamayun" To: qemu-devel@nongnu.org Date: Tue, 23 Jul 2013 11:33:15 +0200 Message-Id: <1374571996-9228-7-git-send-email-m.hamayun@virtualopensystems.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374571996-9228-1-git-send-email-m.hamayun@virtualopensystems.com> References: <1374571996-9228-1-git-send-email-m.hamayun@virtualopensystems.com> X-Gm-Message-State: ALoCoQkBWEwZx7EcyoFQaFEYlmHb164nHBMm6JYNGQjlsdS1d7TbxT1f/d6Ln9E3h4hknwMiUWhI X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 74.125.82.48 Cc: peter.maydell@linaro.org, tech@virtualopensystems.com, kvmarm@lists.cs.columbia.edu Subject: [Qemu-devel] [PATCH v2 6/7] AARCH64: Add SMP support for aarch64 processors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Spyridakis AArch64 uses a cpu-release-addr memory location (defined in the dts) as a way to inform secondary CPUs where to jump to and enter their holding pen. Inject a very simple bootloader that polls this memory location, until the primary CPU sets it to the right address. Signed-off-by: Alexander Spyridakis --- hw/arm/boot.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b9b0beb..efbd984 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -17,6 +17,8 @@ #include "sysemu/device_tree.h" #include "qemu/config-file.h" +#define DSB_INSN 0xf57ff04f +#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ #define KERNEL_ARGS_ADDR 0x100 #ifdef TARGET_AARCH64 @@ -40,6 +42,16 @@ static uint32_t bootloader[] = { 0x00000000 /* .word @Board ID Higher 32-bits -- Placeholder */ }; +static uint32_t smpboot[] = { + 0x180000c5, /* ldr w5, =mbox_value - mbox value for secondary CPUs */ + 0xf94000a4, /* 1: ldr x4, [x5] - Read address to jump to */ + 0xb4ffffe4, /* cbz x4, 1b - Check if mbox value is zero, if yes retry */ + 0xd61f0080, /* br x4 - Branch to given address */ + 0x0, /* padding word */ + 0x0, /* gic_cpu_if_addr */ + 0x8000fff8 /* mbox_value: default mbox value (aka cpu_release_addr) */ +}; + #else #define KERNEL_LOAD_ADDR 0x00010000 #define KERNEL_BOARDID_INDEX 4 @@ -56,7 +68,6 @@ static uint32_t bootloader[] = { 0, /* Address of kernel args. Set by integratorcp_init. */ 0 /* Kernel entry point. Set by integratorcp_init. */ }; -#endif /* Handling for secondary CPU boot in a multicore system. * Unlike the uniprocessor/primary CPU boot, this is platform @@ -72,8 +83,6 @@ static uint32_t bootloader[] = { * for an interprocessor interrupt and polling a configurable * location for the kernel secondary CPU entry point. */ -#define DSB_INSN 0xf57ff04f -#define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */ static uint32_t smpboot[] = { 0xe59f2028, /* ldr r2, gic_cpu_if */ @@ -91,6 +100,7 @@ static uint32_t smpboot[] = { 0, /* gic_cpu_if: base address of GIC CPU interface */ 0 /* bootreg: Boot register address is held here */ }; +#endif static void default_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) @@ -115,8 +125,12 @@ static void default_reset_secondary(ARMCPU *cpu, { CPUARMState *env = &cpu->env; +#ifdef TARGET_AARCH64 + env->pc = info->smp_loader_start; +#else stl_phys_notdirty(info->smp_bootreg_addr, 0); env->regs[15] = info->smp_loader_start; +#endif } #define WRITE_WORD(p, value) do { \