| Message ID | 1374501278-31549-9-git-send-email-pbonzini@redhat.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Jul 22, 2013 at 03:54:18PM +0200, Paolo Bonzini wrote: > This fixes endianness bugs in I/O port access. It looks like it actually did the reverse, ie introducing endianness bugs. With this patch, the pcnet-pci NIC (default NIC card) doesn't work any more on big endian Malta, while it still works on little endian Malta. Reverting this commit fixes the issue for the pcnet card, but it makes the IDE controller to fail, likely due to endianness issues. This is reproducible using the following kernel and the following line: http://ftp.debian.org/debian/dists/wheezy/main/installer-mips/current/images/malta/netboot/vmlinux-3.2.0-4-4kc-malta qemu-system-mips -kernel vmlinux-3.2.0-4-4kc-malta -nographic In that case the boot log is: | [ 0.464000] pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de | [ 0.464000] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003) | [ 0.468000] pcnet32: No access methods Without this patch, the boot log is: | [ 0.524000] pcnet32: pcnet32.c:v1.35 21.Apr.2008 tsbogend@alpha.franken.de | [ 0.524000] PCI: Enabling device 0000:00:0b.0 (0000 -> 0003) | [ 0.524000] pcnet32: PCnet/PCI II 79C970A at 0x1020, 52:54:00:12:34:56 assigned IRQ 10 | [ 0.528000] pcnet32: eth0: registered as PCnet/PCI II 79C970A | [ 0.532000] pcnet32: 1 cards_found > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > hw/mips/gt64xxx_pci.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c > index 5843417..3da2e67 100644 > --- a/hw/mips/gt64xxx_pci.c > +++ b/hw/mips/gt64xxx_pci.c > @@ -304,7 +304,8 @@ static void gt64120_pci_mapping(GT64120State *s) > s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; > isa_mem_base = s->PCI0IO_start; > if (s->PCI0IO_length) { > - isa_mmio_setup(&s->PCI0IO_mem, s->PCI0IO_length); > + memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio", > + get_system_io(), 0, s->PCI0IO_length); > memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, > &s->PCI0IO_mem); > } > -- > 1.8.1.4 > > > >
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 5843417..3da2e67 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -304,7 +304,8 @@ static void gt64120_pci_mapping(GT64120State *s) s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; isa_mem_base = s->PCI0IO_start; if (s->PCI0IO_length) { - isa_mmio_setup(&s->PCI0IO_mem, s->PCI0IO_length); + memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "isa_mmio", + get_system_io(), 0, s->PCI0IO_length); memory_region_add_subregion(get_system_memory(), s->PCI0IO_start, &s->PCI0IO_mem); }
This fixes endianness bugs in I/O port access. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- hw/mips/gt64xxx_pci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)