===================================================================
@@ -1250,8 +1250,7 @@
fext-numeric-literals
C++ ObjC++
-Interpret imaginary, fixed-point, or other gnu number suffix as the corresponding
-number literal rather than a user-defined number literal.
+Interpret imaginary, fixed-point, or other gnu number suffix as the corresponding number literal rather than a user-defined number literal.
idirafter
C ObjC C++ ObjC++ Joined Separate MissingArgError(missing path after %qs)
@@ -1369,13 +1368,11 @@
std=gnu++98
C++ ObjC++
-Conform to the ISO 1998 C++ standard revised by the 2003 technical
-corrigendum with GNU extensions
+Conform to the ISO 1998 C++ standard revised by the 2003 technical corrigendum with GNU extensions
std=gnu++03
C++ ObjC++ Alias(std=gnu++98)
-Conform to the ISO 1998 C++ standard revised by the 2003 technical
-corrigendum with GNU extensions
+Conform to the ISO 1998 C++ standard revised by the 2003 technical corrigendum with GNU extensions
std=gnu++11
C++ ObjC++
===================================================================
@@ -1213,13 +1213,11 @@
fgcse-las
Common Report Var(flag_gcse_las) Init(0) Optimization
-Perform redundant load after store elimination in global common subexpression
-elimination
+Perform redundant load after store elimination in global common subexpression elimination
fgcse-after-reload
Common Report Var(flag_gcse_after_reload) Optimization
-Perform global common subexpression elimination after register allocation
-has finished
+Perform global common subexpression elimination after register allocation has finished
; This option is not documented yet as its semantics will change.
fgraphite
@@ -1232,8 +1230,7 @@
fhoist-adjacent-loads
Common Report Var(flag_hoist_adjacent_loads) Optimization
-Enable hoisting adjacent loads to encourage generating conditional move
-instructions
+Enable hoisting adjacent loads to encourage generating conditional move instructions
floop-parallelize-all
Common Report Var(flag_loop_parallelize_all) Optimization
@@ -1427,13 +1424,11 @@
fira-hoist-pressure
Common Report Var(flag_ira_hoist_pressure) Init(1) Optimization
-Use IRA based register pressure calculation
-in RTL hoist optimizations.
+Use IRA based register pressure calculation in RTL hoist optimizations.
fira-loop-pressure
Common Report Var(flag_ira_loop_pressure)
-Use IRA based register pressure calculation
-in RTL loop optimizations.
+Use IRA based register pressure calculation in RTL loop optimizations.
fira-share-save-slots
Common Report Var(flag_ira_share_save_slots) Init(1)
@@ -1669,8 +1664,7 @@
fprofile-dir=
Common Joined RejectNegative Var(profile_data_prefix)
-Set the top-level directory for storing the profile data.
-The default is 'pwd'.
+Set the top-level directory for storing the profile data. The default is 'pwd'.
fprofile-correction
Common Report Var(flag_profile_correction)
@@ -1884,8 +1878,7 @@
fshrink-wrap
Common Report Var(flag_shrink_wrap) Optimization
-Emit function prologues only before parts of the function that need it,
-rather than at the top of the function.
+Emit function prologues only before parts of the function that need it, rather than at the top of the function.
fsignaling-nans
Common Report Var(flag_signaling_nans) Optimization SetByCombined
@@ -2193,8 +2186,7 @@
fassociative-math
Common Report Var(flag_associative_math) SetByCombined
-Allow optimization for floating-point arithmetic which may change the
-result of the operation due to rounding.
+Allow optimization for floating-point arithmetic which may change the result of the operation due to rounding.
freciprocal-math
Common Report Var(flag_reciprocal_math) SetByCombined
===================================================================
@@ -245,8 +245,7 @@
mfix-cortex-m3-ldrd
Target Report Var(fix_cm3_ldrd) Init(2)
-Avoid overlapping destination and address registers on LDRD instructions
-that may trigger Cortex-M3 errata.
+Avoid overlapping destination and address registers on LDRD instructions that may trigger Cortex-M3 errata.
munaligned-access
Target Report Var(unaligned_access) Init(2)
===================================================================
@@ -53,8 +53,7 @@
mcsync-anomaly
Target Report Var(bfin_csync_anomaly) Init(-1)
-Work around a hardware anomaly by adding a number of NOPs before a
-CSYNC or SSYNC instruction.
+Work around a hardware anomaly by adding a number of NOPs before a CSYNC or SSYNC instruction.
mspecld-anomaly
Target Report Var(bfin_specld_anomaly) Init(-1)
@@ -66,8 +65,7 @@
mleaf-id-shared-library
Target Report Mask(LEAF_ID_SHARED_LIBRARY)
-Generate code that won't be linked against any other ID shared libraries,
-but may be used as a shared library.
+Generate code that won't be linked against any other ID shared libraries, but may be used as a shared library.
mshared-library-id=
Target RejectNegative Joined UInteger Var(bfin_library_id)
===================================================================
@@ -416,13 +416,11 @@
mvzeroupper
Target Report Mask(VZEROUPPER) Save
-Generate vzeroupper instruction before a transfer of control flow out of
-the function.
+Generate vzeroupper instruction before a transfer of control flow out of the function.
mdispatch-scheduler
Target RejectNegative Var(flag_dispatch_scheduler)
-Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 and Haifa scheduling
-is selected.
+Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 and Haifa scheduling is selected.
mprefer-avx128
Target Report Mask(PREFER_AVX128) SAVE
===================================================================
@@ -49,8 +49,7 @@
mstrict-align
Target Report Mask(STRICT_ALIGN) Var(rs6000_isa_flags)
-Align to the base type of the bit-field
-Don't assume that unaligned accesses are handled by the system
+Align to the base type of the bit-field. Don't assume that unaligned accesses are handled by the system
mrelocatable
Target Report Mask(RELOCATABLE) Var(rs6000_isa_flags)
===================================================================
@@ -150,9 +150,7 @@
mbranch-cost=
Target Report Joined RejectNegative UInteger Var(s390_branch_cost) Init(1)
-Set the branch costs for conditional branch instructions. Reasonable
-values are small, non-negative integers. The default branch cost is
-1.
+Set the branch costs for conditional branch instructions. Reasonable values are small, non-negative integers. The default branch cost is 1.
mlra
Target Report Var(s390_lra_flag) Init(1) Save
===================================================================
@@ -198,8 +198,7 @@
mfix-at697f
Target Report RejectNegative Var(sparc_fix_at697f)
-Enable workaround for single erratum of AT697F processor
-(corresponding to erratum #13 of AT697E processor)
+Enable workaround for single erratum of AT697F processor (corresponding to erratum #13 of AT697E processor)
mfix-ut699
Target Report RejectNegative Var(sparc_fix_ut699)
===================================================================
@@ -20,8 +20,7 @@
m32
Target Report RejectNegative
-Compile with 32 bit longs and pointers, which is the only supported
-behavior and thus the flag is ignored.
+Compile with 32 bit longs and pointers, which is the only supported behavior and thus the flag is ignored.
mcpu=
Target RejectNegative Joined Enum(tilepro_cpu) Var(tilepro_cpu) Init(0)