From patchwork Fri Jul 19 19:00:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 260334 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 10A272C007C for ; Sat, 20 Jul 2013 05:01:57 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2A1894A03B; Fri, 19 Jul 2013 21:01:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1Q46yFlXIiRI; Fri, 19 Jul 2013 21:01:30 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 12E4B4A054; Fri, 19 Jul 2013 21:01:15 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B70EA4A025 for ; Fri, 19 Jul 2013 21:00:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c2-xKKQiiAIl for ; Fri, 19 Jul 2013 21:00:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f46.google.com (mail-yh0-f46.google.com [209.85.213.46]) by theia.denx.de (Postfix) with ESMTPS id 192DD4A029 for ; Fri, 19 Jul 2013 21:00:31 +0200 (CEST) Received: by mail-yh0-f46.google.com with SMTP id i57so1631885yha.5 for ; Fri, 19 Jul 2013 12:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=2rFZxDzrpbEhRX9ALKn1DWJZaFSat/IbDy0uE2N1Rj4=; b=0r176FmKyawKbojvpV+rJmv+ilb1fGeiso+sNte0TToxzEz+Xl3Wn1ijQI3DVSXSOi E2uPeYkJID566rAhMI3d4W0GgsUq6AU+W6xtDOA5CY0qUmLcUFwOsGFv/swT0w3wRQLC rJ2sAucE8bqj/Lvv5ZIytlM1b7NN+4t8qBMaZ2cim4995d0Dl0xF3cc3evKtJoXMM1fm Pn/ryzQDSiMH/qt1jfHS/J558Dsih8olLYBNE8YKjYjtouPfMcM8xVrT4cNa313BIRXh MDZzFpn8s8vos/8lDO6ekaqMncVxoUZfDuN5hH2ZoGXvLflLElUMcliNusLtjs5r2ymP xNqQ== X-Received: by 10.236.174.199 with SMTP id x47mr9544281yhl.257.1374260430824; Fri, 19 Jul 2013 12:00:30 -0700 (PDT) Received: from localhost.localdomain (cpe-065-184-250-089.ec.res.rr.com. [65.184.250.89]) by mx.google.com with ESMTPSA id b48sm23285743yhc.8.2013.07.19.12.00.29 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 19 Jul 2013 12:00:30 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Fri, 19 Jul 2013 15:00:26 -0400 Message-Id: <1374260426-9085-6-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374260426-9085-1-git-send-email-trini@ti.com> References: <1374260426-9085-1-git-send-email-trini@ti.com> Subject: [U-Boot] [PATCH 6/6] am335x_evm: am33xx_spl_board_init function and scale core frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 8 ++ board/ti/am335x/board.c | 155 ++++++++++++++++++++++ include/configs/am335x_evm.h | 4 + 3 files changed, 167 insertions(+) diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 89b63d9..834f24f 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -24,6 +24,14 @@ #define CONFIG_SYS_MPUCLK 550 #endif +/* MAIN PLL Fdll supported frequencies */ +#define MPUPLL_M_1000 1000 +#define MPUPLL_M_800 800 +#define MPUPLL_M_720 720 +#define MPUPLL_M_600 600 +#define MPUPLL_M_550 550 +#define MPUPLL_M_300 300 + extern void pll_init(void); extern void enable_emif_clocks(void); extern void enable_dmm_clocks(void); diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index fdbe26c..6544931 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -282,6 +284,159 @@ int spl_start_uboot(void) } #endif +void am33xx_spl_board_init(void) +{ + int mpu_vdd, mpu_pll, sil_rev; + + /* Assume PG 1.0 */ + mpu_pll = MPUPLL_M_720; + + sil_rev = readl(&cdev->deviceid) >> 28; + if (sil_rev == 1) + /* PG 2.0, efuse may not be set. */ + mpu_pll = MPUPLL_M_800; + else if (sil_rev >= 2) { + /* Check what the efuse says our max speed is. */ + int efuse_arm_mpu_max_freq; + efuse_arm_mpu_max_freq = readl(&cdev->efuse_sma); + switch ((efuse_arm_mpu_max_freq & DEVICE_ID_MASK)) { + case AM335X_ZCZ_1000: + mpu_pll = MPUPLL_M_1000; + break; + case AM335X_ZCZ_800: + mpu_pll = MPUPLL_M_800; + break; + case AM335X_ZCZ_720: + mpu_pll = MPUPLL_M_720; + break; + case AM335X_ZCZ_600: + case AM335X_ZCE_600: + mpu_pll = MPUPLL_M_600; + break; + case AM335X_ZCZ_300: + case AM335X_ZCE_300: + mpu_pll = MPUPLL_M_300; + break; + } + } + + if (board_is_bone() || board_is_bone_lt()) { + /* BeagleBone PMIC Code */ + int usb_cur_lim; + + /* + * Only perform PMIC configurations if board rev > A1 + * on Beaglebone White + */ + if (board_is_bone() && !strncmp(header.version, "00A1", 4)) + return; + + if (i2c_probe(TPS65217_CHIP_PM)) + return; + + /* + * On Beaglebone White we need to ensure we have AC power + * before increasing the frequency. + */ + if (board_is_bone()) { + uchar pmic_status_reg; + if (tps65217_reg_read(STATUS, &pmic_status_reg)) + return; + if (!(pmic_status_reg & PWR_SRC_AC_BITMASK)) { + puts("No AC power, disabling frequency switch\n"); + return; + } + } + + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (mpu_pll == MPUPLL_M_1000) { + usb_cur_lim = USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(PROT_LEVEL_NONE, POWER_PATH, + usb_cur_lim, USB_INPUT_CUR_LIMIT_MASK)) + printf("tps65217_reg_write failure\n"); + + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(DEFDCDC2, mpu_vdd)) { + printf("tps65217_voltage_update failure\n"); + return; + } + + /* Set LDO3, LDO4 output voltage to 3.3V */ + if (tps65217_reg_write(PROT_LEVEL_2, DEFLS1, + LDO_VOLTAGE_OUT_3_3, LDO_MASK)) + printf("tps65217_reg_write failure\n"); + + if (tps65217_reg_write(PROT_LEVEL_2, DEFLS2, + LDO_VOLTAGE_OUT_3_3, LDO_MASK)) + printf("tps65217_reg_write failure\n"); + } else { + uchar buf[4]; + + /* + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * MPU frequencies we support we use a CORE voltage of + * 1.1375V. For MPU voltage we need to switch based on + * the frequency we are running at. + */ + if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) + return; + + /* VDD1/2 voltage selection register access by control i/f */ + if (i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + buf, 1)) + return; + + buf[0] |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + if (i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1, + buf, 1)) + return; + + /* Depending on MPU clock we need different MPU VDD */ + + /* Default to PG1.0/PG2.0 values. */ + mpu_vdd = TPS65910_OP_REG_SEL_1_1_3; + + if (sil_rev >= 2) { + switch (mpu_pll) { + case MPUPLL_M_1000: + mpu_vdd = TPS65910_OP_REG_SEL_1_3_2_5; + break; + case MPUPLL_M_800: + mpu_vdd = TPS65910_OP_REG_SEL_1_2_6; + break; + case MPUPLL_M_720: + mpu_vdd = TPS65910_OP_REG_SEL_1_2_0; + break; + case MPUPLL_M_600: + case MPUPLL_M_300: + mpu_vdd = TPS65910_OP_REG_SEL_1_1_3; + break; + } + } + + /* First update MPU voltage. */ + if (tps65910_voltage_update(MPU, mpu_vdd)) + return; + + /* Second, update the CORE voltage. */ + if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) + return; + } + + /* Set MPU Frequency to what we detected now that voltages are set */ + mpu_pll_config_val(mpu_pll); +} #endif /* diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index c5a6d4b..60c87a3 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -289,6 +289,9 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_POWER_TPS65217 +#define CONFIG_POWER_TPS65910 + #define CONFIG_OMAP_GPIO #define CONFIG_BAUDRATE 115200 @@ -352,6 +355,7 @@ #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_YMODEM_SUPPORT