Patchwork [U-Boot,1/2] ARM: tegra: Make cache line size SoC specific

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Submitter Thierry Reding
Date July 18, 2013, 7:13 p.m.
Message ID <1374174821-19981-1-git-send-email-thierry.reding@gmail.com>
Download mbox | patch
Permalink /patch/260128/
State Accepted
Delegated to: Tom Warren
Headers show

Comments

Thierry Reding - July 18, 2013, 7:13 p.m.
From: Thierry Reding <treding@nvidia.com>

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 include/configs/tegra-common.h    | 2 --
 include/configs/tegra114-common.h | 3 +++
 include/configs/tegra20-common.h  | 3 +++
 include/configs/tegra30-common.h  | 3 +++
 4 files changed, 9 insertions(+), 2 deletions(-)
Stephen Warren - July 18, 2013, 9:19 p.m.
On 07/18/2013 01:13 PM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
> isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
> therefore uses a cache line size of 64 bytes. Move the cache line size
> setting to the per-SoC common configuration file.

Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding - July 19, 2013, 2:38 a.m.
On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote:
> On 07/18/2013 01:13 PM, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
> > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
> > therefore uses a cache line size of 64 bytes. Move the cache line size
> > setting to the per-SoC common configuration file.
> 
> Tested-by: Stephen Warren <swarren@nvidia.com>
> Reviewed-by: Stephen Warren <swarren@nvidia.com>

Do these apply to patch 2 of this series as well?

Thierry
Stephen Warren - July 19, 2013, 4:42 a.m.
On 07/18/2013 08:38 PM, Thierry Reding wrote:
> On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote:
>> On 07/18/2013 01:13 PM, Thierry Reding wrote:
>>> From: Thierry Reding <treding@nvidia.com>
>>> 
>>> Currently all Tegra SoCs are assumed to have 32 byte cache
>>> lines. This isn't true for Tegra114, however, which uses 4
>>> Cortex-A15 cores and therefore uses a cache line size of 64
>>> bytes. Move the cache line size setting to the per-SoC common
>>> configuration file.
>> 
>> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by:
>> Stephen Warren <swarren@nvidia.com>
> 
> Do these apply to patch 2 of this series as well?

Yes, the whole series.
Stephen Warren - Aug. 14, 2013, 4:05 p.m.
On 07/18/2013 01:13 PM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
> isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
> therefore uses a cache line size of 64 bytes. Move the cache line size
> setting to the per-SoC common configuration file.

Tom, can these two patches be applied please?

Patch

diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index cb9e7c3..056207b 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -33,8 +33,6 @@ 
 #define CONFIG_TEGRA			/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
 /*
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 44e98e5..c3de9a9 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -18,6 +18,9 @@ 
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * NS16550 Configuration
  */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index d5abecb..b334b33 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -25,6 +25,9 @@ 
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 7ea36be..a72dc13 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -25,6 +25,9 @@ 
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */