From patchwork Thu Jul 18 06:04:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bharat Bhushan X-Patchwork-Id: 260008 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A26BA2C00BF for ; Thu, 18 Jul 2013 16:11:02 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758240Ab3GRGLB (ORCPT ); Thu, 18 Jul 2013 02:11:01 -0400 Received: from mail-db8lp0189.outbound.messaging.microsoft.com ([213.199.154.189]:24457 "EHLO db8outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751629Ab3GRGLA (ORCPT ); Thu, 18 Jul 2013 02:11:00 -0400 Received: from mail133-db8-R.bigfish.com (10.174.8.232) by DB8EHSOBE006.bigfish.com (10.174.4.69) with Microsoft SMTP Server id 14.1.225.22; Thu, 18 Jul 2013 06:10:59 +0000 Received: from mail133-db8 (localhost [127.0.0.1]) by mail133-db8-R.bigfish.com (Postfix) with ESMTP id 646D93E00C3; Thu, 18 Jul 2013 06:10:59 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz1de098h1de097h8275bhz2dh2a8h668h839he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1155h) Received: from mail133-db8 (localhost.localdomain [127.0.0.1]) by mail133-db8 (MessageSwitch) id 1374127856776819_24706; Thu, 18 Jul 2013 06:10:56 +0000 (UTC) Received: from DB8EHSMHS001.bigfish.com (unknown [10.174.8.254]) by mail133-db8.bigfish.com (Postfix) with ESMTP id B947342026E; Thu, 18 Jul 2013 06:10:56 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB8EHSMHS001.bigfish.com (10.174.4.11) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 18 Jul 2013 06:10:56 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.3.136.1; Thu, 18 Jul 2013 06:10:55 +0000 Received: from freescale.com ([10.232.15.72]) by az84smr01.freescale.net (8.14.3/8.14.0) with SMTP id r6I6AoWc019789; Wed, 17 Jul 2013 23:10:51 -0700 Received: by freescale.com (sSMTP sendmail emulation); Thu, 18 Jul 2013 11:34:23 +0530 From: Bharat Bhushan To: , , , CC: Bharat Bhushan , Bharat Bhushan Subject: [PATCH 2/2] kvm: powerpc: set cache coherency only for kernel managed pages Date: Thu, 18 Jul 2013 11:34:16 +0530 Message-ID: <1374127456-9614-2-git-send-email-Bharat.Bhushan@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1374127456-9614-1-git-send-email-Bharat.Bhushan@freescale.com> References: <1374127456-9614-1-git-send-email-Bharat.Bhushan@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org If there is a struct page for the requested mapping then it's normal DDR and the mapping sets "M" bit (coherent, cacheable) else this is treated as I/O and we set "I + G" (cache inhibited, guarded) This helps setting proper TLB mapping for direct assigned device Signed-off-by: Bharat Bhushan --- arch/powerpc/kvm/e500_mmu_host.c | 17 ++++++++++++----- 1 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c index 1c6a9d7..089c227 100644 --- a/arch/powerpc/kvm/e500_mmu_host.c +++ b/arch/powerpc/kvm/e500_mmu_host.c @@ -64,13 +64,20 @@ static inline u32 e500_shadow_mas3_attrib(u32 mas3, int usermode) return mas3; } -static inline u32 e500_shadow_mas2_attrib(u32 mas2, int usermode) +static inline u32 e500_shadow_mas2_attrib(u32 mas2, pfn_t pfn) { + u32 mas2_attr; + + mas2_attr = mas2 & MAS2_ATTRIB_MASK; + + if (!pfn_valid(pfn)) { + mas2_attr |= MAS2_I | MAS2_G; + } else { #ifdef CONFIG_SMP - return (mas2 & MAS2_ATTRIB_MASK) | MAS2_M; -#else - return mas2 & MAS2_ATTRIB_MASK; + mas2_attr |= MAS2_M; #endif + } + return mas2_attr; } /* @@ -313,7 +320,7 @@ static void kvmppc_e500_setup_stlbe( /* Force IPROT=0 for all guest mappings. */ stlbe->mas1 = MAS1_TSIZE(tsize) | get_tlb_sts(gtlbe) | MAS1_VALID; stlbe->mas2 = (gvaddr & MAS2_EPN) | - e500_shadow_mas2_attrib(gtlbe->mas2, pr); + e500_shadow_mas2_attrib(gtlbe->mas2, pfn); stlbe->mas7_3 = ((u64)pfn << PAGE_SHIFT) | e500_shadow_mas3_attrib(gtlbe->mas7_3, pr);