From patchwork Wed Jul 17 16:24:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom Rini X-Patchwork-Id: 259715 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 733262C0079 for ; Thu, 18 Jul 2013 02:25:13 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A27084A09D; Wed, 17 Jul 2013 18:25:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id g+hlVGcmFCct; Wed, 17 Jul 2013 18:25:06 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E16FF4A09E; Wed, 17 Jul 2013 18:25:00 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6538D4A053 for ; Wed, 17 Jul 2013 18:24:51 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QRiMF2vgh6Pa for ; Wed, 17 Jul 2013 18:24:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from mail-yh0-f48.google.com (mail-yh0-f48.google.com [209.85.213.48]) by theia.denx.de (Postfix) with ESMTPS id 7F98A4A054 for ; Wed, 17 Jul 2013 18:24:36 +0200 (CEST) Received: by mail-yh0-f48.google.com with SMTP id z12so748288yhz.21 for ; Wed, 17 Jul 2013 09:24:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; bh=Yn26l2bmx9oqpYxN6XFzTr/0+haVCUhw1fG8DroCmoc=; b=RpNSyKcHi547wNZits6XFaPQDQZ3l+lGThULs4Zb5XuqM8VwZ6Su2Vt/I63V77dxBP WsUuzZDVokV5lBume/jdP8rKlfjdlt6jBkjSKJ3IMK+VZXqdHvN9jjMH+6MZvnYRzHV/ hkG2WAtoNrOGhI8v4X2AjQBq2APcqtxrvVGYwxdPPBGDtVXxlh0knnzBo2FNAno8WtnQ D13ltD3MLLx3cg0KRjKsTsmt5pXBU78kNzPJ+4zCRUywJmYtC8Q1bfOQivr21b1dACfE LVoU4UGGIJSJ0O2mULDZs6JKqSmNnplT1GnlmA+P/KE/OpKluETYKIAdOeuA5lLIwL4k NsOw== X-Received: by 10.236.133.168 with SMTP id q28mr3156273yhi.142.1374078275897; Wed, 17 Jul 2013 09:24:35 -0700 (PDT) Received: from localhost.localdomain (cpe-065-184-250-089.ec.res.rr.com. [65.184.250.89]) by mx.google.com with ESMTPSA id b50sm8766834yhl.1.2013.07.17.09.24.34 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 17 Jul 2013 09:24:34 -0700 (PDT) From: Tom Rini To: u-boot@lists.denx.de Date: Wed, 17 Jul 2013 12:24:30 -0400 Message-Id: <1374078270-20098-2-git-send-email-trini@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1374078270-20098-1-git-send-email-trini@ti.com> References: <1374078270-20098-1-git-send-email-trini@ti.com> Subject: [U-Boot] [PATCH 1/1] board/ti/am335x/README: Document NAND programming X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The AM335x GP EVM ships with NAND. Document programming of the chip including the redundant locations that the ROM will check. Signed-off-by: Tom Rini --- board/ti/am335x/README | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index ccc5e16..3444d7e 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -13,6 +13,31 @@ documented in TI's reference designs: - AM335x EVM SK - Beaglebone White - Beaglebone Black +' +NAND +==== + +The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In +this example to program the NAND we assume that an SD card has been +inserted with the files to write in the first SD slot and that mtdparts +have been configured correctly for the board. As a time saving measure we +load MLO into memory in one location, copy it into the three locatations +that the ROM checks for additional valid copies, then load U-Boot into +memory. We then write that whole section of memory to NAND. + +U-Boot # mmc rescan +U-Boot # env default -f -a +U-Boot # nand erase.chip +U-Boot # saveenv +U-Boot # load mmc 0 81000000 MLO +U-Boot # cp.b 81000000 81020000 20000 +U-Boot # cp.b 81000000 81040000 20000 +U-Boot # cp.b 81000000 81060000 20000 +U-Boot # load mmc 0 81080000 u-boot.img +U-Boot # nand write 81000000 0 260000 +U-Boot # load mmc 0 ${loadaddr} uImage +U-Boot # nand erase.part kernel +U-Boot # nand write ${loadaddr} kernel 500000 Falcon Mode ===========