From patchwork Tue Jul 16 16:55:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Bergner X-Patchwork-Id: 259470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 4C99F2C0107 for ; Wed, 17 Jul 2013 02:55:27 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; q=dns; s= default; b=DB+T/kT1fpKw3qp4r6ibWpADxvxv6U/tmOu87B1wksIUwhGZDiwfH sN+5geKyq2hCamqmdFT3/9E1/0a4oLTxbcSh3+ayz31izeSUso+GcQqZvadVMZur iRXrcfQhPny/0i27dwaSglZASkW9en6gzWNfu0lGC1sopYwY57pqOw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:content-transfer-encoding; s=default; bh=0LCg9IStaYG/HVQLXr1Vq1ofUlw=; b=tJJKNlqCYRQObB8zwAP5r3JS/ctC dV076b02l94u8zLvMRfDaKaTscYaYrIjethS2VzGOD9jh+LKaBelwo0U56/pyYkX cPgIRdaaKNFENLJan9Sl0UcDKivTfznp219lPxxnfyLye0scij58gBoufCU0Tp5Z TDkOTlDI4YR2H90= Received: (qmail 824 invoked by alias); 16 Jul 2013 16:55:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 810 invoked by uid 89); 16 Jul 2013 16:55:20 -0000 X-Spam-SWARE-Status: No, score=-4.0 required=5.0 tests=AWL, BAYES_00, KHOP_THREADED, RCVD_IN_DNSWL_MED, RCVD_IN_HOSTKARMA_W, RDNS_NONE, SPF_PASS, TW_SF autolearn=ham version=3.3.1 Received: from Unknown (HELO e28smtp02.in.ibm.com) (122.248.162.2) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 16 Jul 2013 16:55:19 +0000 Received: from /spool/local by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 16 Jul 2013 22:16:23 +0530 Received: from d28relay05.in.ibm.com (d28relay05.in.ibm.com [9.184.220.62]) by d28dlp03.in.ibm.com (Postfix) with ESMTP id 5372F1258043 for ; Tue, 16 Jul 2013 22:24:26 +0530 (IST) Received: from d28av01.in.ibm.com (d28av01.in.ibm.com [9.184.220.63]) by d28relay05.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r6GGt3LZ27918402 for ; Tue, 16 Jul 2013 22:25:04 +0530 Received: from d28av01.in.ibm.com (loopback [127.0.0.1]) by d28av01.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id r6GGt5QW022195 for ; Tue, 16 Jul 2013 16:55:05 GMT Received: from [192.168.1.113] (vorma.rchland.ibm.com [9.10.86.174]) by d28av01.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id r6GGt17d021951; Tue, 16 Jul 2013 16:55:02 GMT Subject: Re: [PATCH, rs6000, libitm] Enable Hardware Transactional Memory (HTM) support on Power From: Peter Bergner To: Jakub Jelinek Cc: David Edelsohn , "gcc-patches@gcc.gnu.org" , Richard Henderson , Michael Meissner , Pat Haugen In-Reply-To: <20130715203525.GT2475@laptop.redhat.com> References: <1372734758.4736.149.camel@otta> <1373901800.4538.122.camel@otta> <1373909158.4538.156.camel@otta> <20130715184412.GN2475@laptop.redhat.com> <20130715191359.GQ2475@laptop.redhat.com> <1373917616.4538.165.camel@otta> <20130715203525.GT2475@laptop.redhat.com> Date: Tue, 16 Jul 2013 11:55:00 -0500 Message-ID: <1373993700.4538.194.camel@otta> Mime-Version: 1.0 X-TM-AS-MML: No X-Content-Scanned: Fidelis XPS MAILER x-cbid: 13071616-5816-0000-0000-000008F08FCC On Mon, 2013-07-15 at 22:35 +0200, Jakub Jelinek wrote: > On Mon, Jul 15, 2013 at 02:46:56PM -0500, Peter Bergner wrote: > > > I'd say something like (but, untested and can't test it right now (and no > > > access to power8 anyway)): > > > > Do we also need to update DWARF_REG_TO_UNWIND_COLUMN similarly, which > > also uses FIRST_PSEUDO_REGISTER when the dwarf reg is an SPE synthetic > > register? > > Looks like it. Guess that "- 1" in there: > #define DWARF_REG_TO_UNWIND_COLUMN(r) \ > ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) > stands for the sfp register and thus it would be "- 4". > > > Or should we just break the dependence on FIRST_PSEUDO_REGISTER > > altogether so this type of thing doesn't happen again? Otherwise, we > > should place a comment at the definition of FIRST_PSEUDO_REGISTER > > warning of it's use in DWARF_FRAME_REGISTER. > > That is surely an option too. Or use (DWARF_FRAME_REGISTERS - 32) > in the DWARF_REG_TO_UNWIND_COLUMN definition instead of the current > FIRST_PSEUDO_REGISTER - 1, and perhaps make DWARF_FRAME_REGISTERS > just a number (independent on FIRST_PSEUDO_REGISTER). > Guess this depends on what David prefers. I like the idea of removing FIRST_PSEUDO_REGISTER from the definition of DWARF_REG_TO_UNWIND_COLUMN. I'll still let David decide whether he wants DWARF_FRAME_REGISTERS to be just a number of computed off of FIRST_PSEUDO_REGISTER. In the meantime, I'll bootstrap and regtest your patch along with the DWARF_REG_TO_UNWIND_COLUMN change. Peter * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTERS): Mention HTM registers in the comment. (DWARF_FRAME_REGISTERS): Subtract also the 3 HTM registers. (DWARF_REG_TO_UNWIND_COLUMN): Use DWARF_FRAME_REGISTERS rather than FIRST_PSEUDO_REGISTERS. Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 200985) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -892,15 +892,17 @@ enum data_align { align_abi, align_opt, in inline functions. Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame - pointer, which is eventually eliminated in favor of SP or FP. */ + pointer, which is eventually eliminated in favor of SP or FP. + The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ + #define FIRST_PSEUDO_REGISTER 117 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 /* Add 32 dwarf columns for synthetic SPE registers. */ -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) +#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame @@ -916,7 +918,7 @@ enum data_align { align_abi, align_opt, We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) + ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO)