From patchwork Tue Jul 16 13:41:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 259419 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "localhost", Issuer "www.qmailtoaster.com" (not verified)) by ozlabs.org (Postfix) with ESMTPS id 1BCE92C0158 for ; Tue, 16 Jul 2013 23:42:20 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; q=dns; s=default; b=iFM55IJvCKipdpP4 WTcOZCd0PAK1P65FN8aV2EGLzn5DBZf6KUM3wsDtq8TKdfKMEUy4B7Zsa2c8BvBR hSg7nnjkTIYCyOuWRT3tUgdWq2EKGriDJzhLimCLCW6ATBzxiyPRlmcaozHaeEyo liiECMAt90D2Y825nn7I/7xsQtw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:in-reply-to:message-id:references :mime-version:content-type; s=default; bh=lSLycLD+6F5DGMw8oRoLHl 66OzI=; b=T1PWmhGxSGYaNsgj85v6LDRoKMlbRV4oV8iE79S2DjF4UGgqKJX82H VeLr1l3cXr8ODhE6cd8/5IXtRwq0Zag+22zenxaa4VszJa0rCWPEB2xjQWgT0xj+ Y+30dKLCMXl9Z7cRBC4ffQDc/ZZ7PuNCUUYNfmGYtveJU+UqH51wk= Received: (qmail 6400 invoked by alias); 16 Jul 2013 13:42:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6391 invoked by uid 89); 16 Jul 2013 13:42:10 -0000 X-Spam-SWARE-Status: No, score=-2.8 required=5.0 tests=AWL, BAYES_50, KHOP_RCVD_UNTRUST, KHOP_THREADED, RCVD_IN_HOSTKARMA_W, RCVD_IN_HOSTKARMA_WL, RDNS_NONE autolearn=no version=3.3.1 Received: from Unknown (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 16 Jul 2013 13:42:08 +0000 Received: from svr-orw-exc-10.mgc.mentorg.com ([147.34.98.58]) by relay1.mentorg.com with esmtp id 1Uz5Vw-0006Jb-Lf from Maciej_Rozycki@mentor.com ; Tue, 16 Jul 2013 06:42:00 -0700 Received: from SVR-IES-FEM-02.mgc.mentorg.com ([137.202.0.106]) by SVR-ORW-EXC-10.mgc.mentorg.com with Microsoft SMTPSVC(6.0.3790.4675); Tue, 16 Jul 2013 06:42:00 -0700 Received: from [172.30.64.18] (137.202.0.76) by SVR-IES-FEM-02.mgc.mentorg.com (137.202.0.106) with Microsoft SMTP Server id 14.2.247.3; Tue, 16 Jul 2013 14:41:59 +0100 Date: Tue, 16 Jul 2013 14:41:52 +0100 From: "Maciej W. Rozycki" To: Richard Sandiford CC: Steve Ellcey , "gcc-patches@gcc.gnu.org" Subject: [PATCH v2] MIPS: MIPS32r2 FP MADD instruction set support In-Reply-To: Message-ID: References: <871ucavy5x.fsf@talisman.default> <1C0E790D7E4C75418622FD04CC2A1172015D6DAF@bamail02.ba.imgtec.org> <87obf5eedo.fsf@talisman.default> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 On Wed, 27 Feb 2013, Maciej W. Rozycki wrote: > > Maciej, in that case, the rest of the patch is OK for 4.9, thanks. > > I will apply in due course then, thanks for your review. Regrettably after further investigation I have realised the change I proposed inadvertently enables more than just the FP MADD instruction set. It also enables the FP indexed memory access instructions. While that itself is not a bad change, it will better be discussed separately. Here's a new version that does not enable anything beyond the FP MADD instruction set. While making this update I also noticed and fixed a place in mips_rtx_costs where ISA_HAS_FP4 was used where ISA_HAS_FP_MADD* should be. I have regression-tested this change with the mips-linux-gnu target and the mips32r2/o32 multilib. I have also verified that the instructions affected were absent across the binaries produced by the testsuite before applying this change and present afterwards. For some reason only MADD.S, MADD.D, MSUB.S and MSUB.D instructions were produced though -- it looks like none of NMADD.S, NMADD.D, NMSUB.S and NMSUB.D instructions has coverage in our testsuite. I have also verified no FP indexed memory access instructions were produced whether with or without the patch applied. And for safety I have also likewise checked the reciprocals that I'll handle separately as well. OK to apply? 2013-07-16 Maciej W. Rozycki gcc/ * config/mips/mips.h (ISA_HAS_FP4): Correct formatting. (ISA_HAS_FP_MADD4_MSUB4): Also enable for ISA_MIPS32R2. (ISA_HAS_NMADD4_NMSUB4): Remove the MODE argument; rewrite in terms of ISA_HAS_FP4, and also enable for ISA_MIPS32R2. (ISA_HAS_NMADD3_NMSUB3): Remove the MODE argument. * config/mips/mips.c (mips_rtx_costs) : Check for ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3 rather than ISA_HAS_FP4. : Update according to changes to ISA_HAS_NMADD4_NMSUB4 and ISA_HAS_NMADD3_NMSUB3. * config/mips/mips.md (nmadd4, nmadd3): Likewise. (nmadd4_fastmath, nmadd3_fastmath): Likewise. (nmsub4, nmsub3): Likewise. (nmsub4_fastmath, nmsub3_fastmath): Likewise. Maciej Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.c =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.c 2013-07-13 00:59:53.000000000 +0100 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.c 2013-07-13 01:24:21.590274806 +0100 @@ -3857,7 +3857,7 @@ mips_rtx_costs (rtx x, int code, int out case MINUS: if (float_mode_p - && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) + && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3) && TARGET_FUSED_MADD && !HONOR_NANS (mode) && !HONOR_SIGNED_ZEROS (mode)) @@ -3890,7 +3890,7 @@ mips_rtx_costs (rtx x, int code, int out { /* If this is part of a MADD or MSUB, treat the PLUS as being free. */ - if (ISA_HAS_FP4 + if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3) && TARGET_FUSED_MADD && GET_CODE (XEXP (x, 0)) == MULT) *total = 0; @@ -3909,7 +3909,7 @@ mips_rtx_costs (rtx x, int code, int out case NEG: if (float_mode_p - && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) + && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3) && TARGET_FUSED_MADD && !HONOR_NANS (mode) && HONOR_SIGNED_ZEROS (mode)) Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.h =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.h 2013-07-13 00:59:53.000000000 +0100 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.h 2013-07-13 01:12:22.560918747 +0100 @@ -881,7 +881,7 @@ struct mips_cpu_info { FP madd and msub instructions, and the FP recip and recip sqrt instructions. */ #define ISA_HAS_FP4 ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && TARGET_FLOAT64) \ + || (ISA_MIPS32R2 && TARGET_FLOAT64) \ || ISA_MIPS64 \ || ISA_MIPS64R2) \ && !TARGET_MIPS16) @@ -903,24 +903,20 @@ struct mips_cpu_info { #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */ -#define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4 +#define ISA_HAS_FP_MADD4_MSUB4 (ISA_HAS_FP4 \ + || (ISA_MIPS32R2 && !TARGET_MIPS16)) /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */ #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF /* ISA has floating-point nmadd and nmsub instructions 'd = -((a * b) [+-] c)'. */ -#define ISA_HAS_NMADD4_NMSUB4(MODE) \ - ((ISA_MIPS4 \ - || (ISA_MIPS32R2 && (MODE) == V2SFmode) \ - || ISA_MIPS64 \ - || ISA_MIPS64R2) \ - && !TARGET_MIPS16) +#define ISA_HAS_NMADD4_NMSUB4 (ISA_HAS_FP4 \ + || (ISA_MIPS32R2 && !TARGET_MIPS16)) /* ISA has floating-point nmadd and nmsub instructions 'c = -((a * b) [+-] c)'. */ -#define ISA_HAS_NMADD3_NMSUB3(MODE) \ - TARGET_LOONGSON_2EF +#define ISA_HAS_NMADD3_NMSUB3 TARGET_LOONGSON_2EF /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \ Index: gcc-fsf-trunk-quilt/gcc/config/mips/mips.md =================================================================== --- gcc-fsf-trunk-quilt.orig/gcc/config/mips/mips.md 2013-07-13 00:59:53.000000000 +0100 +++ gcc-fsf-trunk-quilt/gcc/config/mips/mips.md 2013-07-13 01:00:40.529942011 +0100 @@ -2367,7 +2367,7 @@ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") (match_operand:ANYF 2 "register_operand" "f")) (match_operand:ANYF 3 "register_operand" "f"))))] - "ISA_HAS_NMADD4_NMSUB4 (mode) + "ISA_HAS_NMADD4_NMSUB4 && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2382,7 +2382,7 @@ (mult:ANYF (match_operand:ANYF 1 "register_operand" "f") (match_operand:ANYF 2 "register_operand" "f")) (match_operand:ANYF 3 "register_operand" "0"))))] - "ISA_HAS_NMADD3_NMSUB3 (mode) + "ISA_HAS_NMADD3_NMSUB3 && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2397,7 +2397,7 @@ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) (match_operand:ANYF 2 "register_operand" "f")) (match_operand:ANYF 3 "register_operand" "f")))] - "ISA_HAS_NMADD4_NMSUB4 (mode) + "ISA_HAS_NMADD4_NMSUB4 && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2412,7 +2412,7 @@ (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")) (match_operand:ANYF 2 "register_operand" "f")) (match_operand:ANYF 3 "register_operand" "0")))] - "ISA_HAS_NMADD3_NMSUB3 (mode) + "ISA_HAS_NMADD3_NMSUB3 && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2427,7 +2427,7 @@ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") (match_operand:ANYF 3 "register_operand" "f")) (match_operand:ANYF 1 "register_operand" "f"))))] - "ISA_HAS_NMADD4_NMSUB4 (mode) + "ISA_HAS_NMADD4_NMSUB4 && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2442,7 +2442,7 @@ (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") (match_operand:ANYF 3 "register_operand" "f")) (match_operand:ANYF 1 "register_operand" "0"))))] - "ISA_HAS_NMADD3_NMSUB3 (mode) + "ISA_HAS_NMADD3_NMSUB3 && TARGET_FUSED_MADD && HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2457,7 +2457,7 @@ (match_operand:ANYF 1 "register_operand" "f") (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") (match_operand:ANYF 3 "register_operand" "f"))))] - "ISA_HAS_NMADD4_NMSUB4 (mode) + "ISA_HAS_NMADD4_NMSUB4 && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)" @@ -2472,7 +2472,7 @@ (match_operand:ANYF 1 "register_operand" "f") (mult:ANYF (match_operand:ANYF 2 "register_operand" "f") (match_operand:ANYF 3 "register_operand" "0"))))] - "ISA_HAS_NMADD3_NMSUB3 (mode) + "ISA_HAS_NMADD3_NMSUB3 && TARGET_FUSED_MADD && !HONOR_SIGNED_ZEROS (mode) && !HONOR_NANS (mode)"