From patchwork Wed Jul 10 10:20:48 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Riku Voipio X-Patchwork-Id: 258001 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3D97A2C02CE for ; Wed, 10 Jul 2013 20:21:43 +1000 (EST) Received: from localhost ([::1]:51859 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwrWl-0000cE-4L for incoming@patchwork.ozlabs.org; Wed, 10 Jul 2013 06:21:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39628) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwrWE-0000Wn-Jr for qemu-devel@nongnu.org; Wed, 10 Jul 2013 06:21:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UwrW3-000075-9b for qemu-devel@nongnu.org; Wed, 10 Jul 2013 06:21:06 -0400 Received: from afflict.kos.to ([92.243.29.197]:38808) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwrW3-00006R-2C for qemu-devel@nongnu.org; Wed, 10 Jul 2013 06:20:55 -0400 Received: from kos.to (unknown [193.120.41.118]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by afflict.kos.to (Postfix) with ESMTPSA id A2F652654C for ; Wed, 10 Jul 2013 12:20:52 +0200 (CEST) Received: from voipio (uid 1000) (envelope-from voipio@kos.to) id 5e0679 by kos.to (DragonFly Mail Agent); Wed, 10 Jul 2013 13:20:51 +0300 From: riku.voipio@linaro.org To: qemu-devel@nongnu.org Date: Wed, 10 Jul 2013 13:20:48 +0300 Message-Id: <023b0ae33be6ce2e60d75d2b54a3d2cea6b6020e.1373051589.git.riku.voipio@linaro.org> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 92.243.29.197 Cc: Peter Maydell Subject: [Qemu-devel] [PATCH 5/7] user-exec.c: Set is_write correctly in the ARM cpu_signal_handler() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Maydell In the ARM implementation of cpu_signal_handler(), set is_write correctly using the FSR value which the kernel passes us in the error_code field of uc_mcontext. Since the WnR bit of the FSR was only introduced in ARMv6, this means that v5 cores will continue to behave as before this patch, but they are not really supported as hosts for linux-user mode anyway since they do not have the modern behaviour for unaligned accesses. Signed-off-by: Peter Maydell Message-id: 1370352705-27590-1-git-send-email-peter.maydell@linaro.org --- user-exec.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/user-exec.c b/user-exec.c index fa7f1f1..57c8e8d 100644 --- a/user-exec.c +++ b/user-exec.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "disas/disas.h" #include "tcg.h" +#include "qemu/bitops.h" #undef EAX #undef ECX @@ -441,8 +442,11 @@ int cpu_signal_handler(int host_signum, void *pinfo, #else pc = uc->uc_mcontext.arm_pc; #endif - /* XXX: compute is_write */ - is_write = 0; + + /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or + * later processor; on v5 we will always report this as a read). + */ + is_write = extract32(uc->uc_mcontext.error_code, 11, 1); return handle_cpu_signal(pc, (unsigned long)info->si_addr, is_write, &uc->uc_sigmask, puc);