Patchwork [5/7] user-exec.c: Set is_write correctly in the ARM cpu_signal_handler()

login
register
mail settings
Submitter riku.voipio@linaro.org
Date July 10, 2013, 10:20 a.m.
Message ID <023b0ae33be6ce2e60d75d2b54a3d2cea6b6020e.1373051589.git.riku.voipio@linaro.org>
Download mbox | patch
Permalink /patch/258001/
State New
Headers show

Comments

riku.voipio@linaro.org - July 10, 2013, 10:20 a.m.
From: Peter Maydell <peter.maydell@linaro.org>

In the ARM implementation of cpu_signal_handler(), set is_write
correctly using the FSR value which the kernel passes us in the
error_code field of uc_mcontext. Since the WnR bit of the FSR was
only introduced in ARMv6, this means that v5 cores will continue
to behave as before this patch, but they are not really supported
as hosts for linux-user mode anyway since they do not have the
modern behaviour for unaligned accesses.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1370352705-27590-1-git-send-email-peter.maydell@linaro.org
---
 user-exec.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

Patch

diff --git a/user-exec.c b/user-exec.c
index fa7f1f1..57c8e8d 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -20,6 +20,7 @@ 
 #include "cpu.h"
 #include "disas/disas.h"
 #include "tcg.h"
+#include "qemu/bitops.h"
 
 #undef EAX
 #undef ECX
@@ -441,8 +442,11 @@  int cpu_signal_handler(int host_signum, void *pinfo,
 #else
     pc = uc->uc_mcontext.arm_pc;
 #endif
-    /* XXX: compute is_write */
-    is_write = 0;
+
+    /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
+     * later processor; on v5 we will always report this as a read).
+     */
+    is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                              is_write,
                              &uc->uc_sigmask, puc);