| Message ID | 1373407124-16695-1-git-send-email-b45784@freescale.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
Hi Pardeep, On 09/07/2013 23:58, Pardeep Kumar Singla wrote: > Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com> > --- > board/freescale/mx6qsabresd/mx6qsabresd.c | 92 ++++++++++++++++++++++++++++- > include/configs/mx6qsabre_common.h | 3 +- > include/configs/mx6qsabresd.h | 13 ++++ > 3 files changed, 106 insertions(+), 2 deletions(-) > Your patch shares a lot of code with mx6qsabrelite. Can we factorize the common code ? > diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c > index 2529826..301fd1b 100644 > --- a/board/freescale/mx6qsabresd/mx6qsabresd.c > +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c > @@ -31,6 +31,11 @@ > #include <fsl_esdhc.h> > #include <miiphy.h> > #include <netdev.h> > +#include <asm/arch/crm_regs.h> > +#include <asm/arch/crm_regs.h> > +#include <ipu_pixfmt.h> > +#include <linux/fb.h> > +#include <asm/arch/mxc_hdmi.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -133,6 +138,80 @@ static void setup_iomux_uart(void) > imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); > } > > +#if defined(CONFIG_VIDEO_IPUV3) > +static void enable_hdmi(void) > +{ > + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; > + u8 reg; > + reg = readb(&hdmi->phy_conf0); > + reg |= HDMI_PHY_CONF0_PDZ_MASK; > + writeb(reg, &hdmi->phy_conf0); > + udelay(3000); > + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; > + writeb(reg, &hdmi->phy_conf0); > + udelay(3000); > + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; > + writeb(reg, &hdmi->phy_conf0); > + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); > +} > + For example, enable:hdmi is really identical to the same function of the sabrelite. > +static struct fb_videomode const hdmi = { > + .name = "HDMI", > + .refresh = 60, > + .xres = 1024, > + .yres = 768, > + .pixclock = 15385, > + .left_margin = 220, > + .right_margin = 40, > + .upper_margin = 21, > + .lower_margin = 7, > + .hsync_len = 60, > + .vsync_len = 10, > + .sync = FB_SYNC_EXT, > + .vmode = FB_VMODE_NONINTERLACED > +}; > + > +int board_video_skip(void) > +{ > + int ret; > + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); > + if (ret) > + printf("HDMI cannot be configured: %d\n", ret); > + enable_hdmi(); > + return ret; > +} > + > +static void setup_display(void) > +{ > + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; > + int reg; > + > + /* Turn on IPU clock */ > + reg = readl(&mxc_ccm->CCGR3); > + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; > + writel(reg, &mxc_ccm->CCGR3); > + /* Turn on HDMI PHY clock */ > + reg = readl(&mxc_ccm->CCGR2); > + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| > + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; > + writel(reg, &mxc_ccm->CCGR2); > + /* clear HDMI PHY reset */ > + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); > + reg = readl(&mxc_ccm->chsccdr); > + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| > + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| > + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); > + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 > + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)| > + (CHSCCDR_PODF_DIVIDE_BY_3 > + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) > + | (CHSCCDR_IPU_PRE_CLK_540M_PFD > + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); > + writel(reg, &mxc_ccm->chsccdr); > +} > +#endif /* CONFIG_VIDEO_IPUV3 */ setup_display has also some common parts with the same function for sabrelite. Any way to factorize code ? Best regards, Stefano Babic
Hi Stefano, Sure, I can try this on my side. I will let you know about this shortly. Thank you very much for giving your input. Thanks & Regards, Pardeep Singla -----Original Message----- From: Stefano Babic [mailto:sbabic@denx.de] Sent: Wednesday, July 10, 2013 8:25 AM To: Kumar Singla Pardeep-B45784 Cc: sbabic@denx.de; Estevam Fabio-R49496; u-boot@lists.denx.de Subject: Re: [PATCH]mx6qsabresd: Add splash screen support via HDMI Hi Pardeep, On 09/07/2013 23:58, Pardeep Kumar Singla wrote: > Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com> > --- > board/freescale/mx6qsabresd/mx6qsabresd.c | 92 ++++++++++++++++++++++++++++- > include/configs/mx6qsabre_common.h | 3 +- > include/configs/mx6qsabresd.h | 13 ++++ > 3 files changed, 106 insertions(+), 2 deletions(-) > Your patch shares a lot of code with mx6qsabrelite. Can we factorize the common code ? > diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c > b/board/freescale/mx6qsabresd/mx6qsabresd.c > index 2529826..301fd1b 100644 > --- a/board/freescale/mx6qsabresd/mx6qsabresd.c > +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c > @@ -31,6 +31,11 @@ > #include <fsl_esdhc.h> > #include <miiphy.h> > #include <netdev.h> > +#include <asm/arch/crm_regs.h> > +#include <asm/arch/crm_regs.h> > +#include <ipu_pixfmt.h> > +#include <linux/fb.h> > +#include <asm/arch/mxc_hdmi.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -133,6 +138,80 @@ static void setup_iomux_uart(void) > imx_iomux_v3_setup_multiple_pads(uart1_pads, > ARRAY_SIZE(uart1_pads)); } > > +#if defined(CONFIG_VIDEO_IPUV3) > +static void enable_hdmi(void) > +{ > + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; > + u8 reg; > + reg = readb(&hdmi->phy_conf0); > + reg |= HDMI_PHY_CONF0_PDZ_MASK; > + writeb(reg, &hdmi->phy_conf0); > + udelay(3000); > + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; > + writeb(reg, &hdmi->phy_conf0); > + udelay(3000); > + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; > + writeb(reg, &hdmi->phy_conf0); > + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); } > + For example, enable:hdmi is really identical to the same function of the sabrelite. > +static struct fb_videomode const hdmi = { > + .name = "HDMI", > + .refresh = 60, > + .xres = 1024, > + .yres = 768, > + .pixclock = 15385, > + .left_margin = 220, > + .right_margin = 40, > + .upper_margin = 21, > + .lower_margin = 7, > + .hsync_len = 60, > + .vsync_len = 10, > + .sync = FB_SYNC_EXT, > + .vmode = FB_VMODE_NONINTERLACED > +}; > + > +int board_video_skip(void) > +{ > + int ret; > + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); > + if (ret) > + printf("HDMI cannot be configured: %d\n", ret); > + enable_hdmi(); > + return ret; > +} > + > +static void setup_display(void) > +{ > + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; > + int reg; > + > + /* Turn on IPU clock */ > + reg = readl(&mxc_ccm->CCGR3); > + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; > + writel(reg, &mxc_ccm->CCGR3); > + /* Turn on HDMI PHY clock */ > + reg = readl(&mxc_ccm->CCGR2); > + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| > + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; > + writel(reg, &mxc_ccm->CCGR2); > + /* clear HDMI PHY reset */ > + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); > + reg = readl(&mxc_ccm->chsccdr); > + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| > + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| > + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); > + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 > + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)| > + (CHSCCDR_PODF_DIVIDE_BY_3 > + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) > + | (CHSCCDR_IPU_PRE_CLK_540M_PFD > + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); > + writel(reg, &mxc_ccm->chsccdr); > +} > +#endif /* CONFIG_VIDEO_IPUV3 */ setup_display has also some common parts with the same function for sabrelite. Any way to factorize code ? Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic@denx.de =====================================================================
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index 2529826..301fd1b 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -31,6 +31,11 @@ #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/crm_regs.h> +#include <ipu_pixfmt.h> +#include <linux/fb.h> +#include <asm/arch/mxc_hdmi.h> DECLARE_GLOBAL_DATA_PTR; @@ -133,6 +138,80 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } +#if defined(CONFIG_VIDEO_IPUV3) +static void enable_hdmi(void) +{ + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + u8 reg; + reg = readb(&hdmi->phy_conf0); + reg |= HDMI_PHY_CONF0_PDZ_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_ENTMDS_MASK; + writeb(reg, &hdmi->phy_conf0); + udelay(3000); + reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; + writeb(reg, &hdmi->phy_conf0); + writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); +} + +static struct fb_videomode const hdmi = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED +}; + +int board_video_skip(void) +{ + int ret; + ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); + if (ret) + printf("HDMI cannot be configured: %d\n", ret); + enable_hdmi(); + return ret; +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; + int reg; + + /* Turn on IPU clock */ + reg = readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET; + writel(reg, &mxc_ccm->CCGR3); + /* Turn on HDMI PHY clock */ + reg = readl(&mxc_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| + MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; + writel(reg, &mxc_ccm->CCGR2); + /* clear HDMI PHY reset */ + writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); + reg = readl(&mxc_ccm->chsccdr); + reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)| + (CHSCCDR_PODF_DIVIDE_BY_3 + << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + | (CHSCCDR_IPU_PRE_CLK_540M_PFD + << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->chsccdr); +} +#endif /* CONFIG_VIDEO_IPUV3 */ + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, @@ -257,10 +336,21 @@ int board_eth_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart(); - +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_init(void) { /* address of boot parameters */ diff --git a/include/configs/mx6qsabre_common.h b/include/configs/mx6qsabre_common.h index bfaa420..438cb83 100644 --- a/include/configs/mx6qsabre_common.h +++ b/include/configs/mx6qsabre_common.h @@ -21,6 +21,7 @@ #define CONFIG_MX6Q #include "mx6_common.h" +#include <asm/sizes.h> #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -33,7 +34,7 @@ #define CONFIG_REVISION_TAG /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h index 44f07cb..5e561eb 100644 --- a/include/configs/mx6qsabresd.h +++ b/include/configs/mx6qsabresd.h @@ -26,6 +26,19 @@ #include "mx6qsabre_common.h" +/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_IPUV3_CLK 260000000 + #define CONFIG_SYS_FSL_USDHC_NUM 3 #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */
Signed-off-by: Pardeep Kumar Singla <b45784@freescale.com> --- board/freescale/mx6qsabresd/mx6qsabresd.c | 92 ++++++++++++++++++++++++++++- include/configs/mx6qsabre_common.h | 3 +- include/configs/mx6qsabresd.h | 13 ++++ 3 files changed, 106 insertions(+), 2 deletions(-)