From patchwork Wed Jul 10 04:21:42 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Crosthwaite X-Patchwork-Id: 257963 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 041382C0209 for ; Wed, 10 Jul 2013 14:27:08 +1000 (EST) Received: from localhost ([::1]:40387 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Uwlzd-00036b-SW for incoming@patchwork.ozlabs.org; Wed, 10 Jul 2013 00:27:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33994) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwlzL-00031G-SQ for qemu-devel@nongnu.org; Wed, 10 Jul 2013 00:26:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UwlzK-0002J5-W1 for qemu-devel@nongnu.org; Wed, 10 Jul 2013 00:26:47 -0400 Received: from mail-pa0-f53.google.com ([209.85.220.53]:50907) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UwlzK-0002Iw-P1 for qemu-devel@nongnu.org; Wed, 10 Jul 2013 00:26:46 -0400 Received: by mail-pa0-f53.google.com with SMTP id tj12so6222840pac.40 for ; Tue, 09 Jul 2013 21:26:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=J5cMqm7MC/TTO5InHEyhb3PR/riQOqhkbeSCPeNulck=; b=puCSwPcvJ32cdBexZK0lHsx7BXMqvfMkpY+e+vkI9tLoLknUnE6o76EIGtY4dR/ZIL WReM4aChQ805R2QswT+CxsrYxqP+QOBUskfhqr0hDxSBRPEPEsFeg/0Sg8y3TKK3CdhW 3BwhSn/PV3sIFC/J1Rklqm54vyYvFW3xKKJWG3dz18Hy28vXaLyflsaRwrvHryIH+y12 i8bow4SEbh+wMckS+2zlDK38Xis129wDyNRFYCJ7eTP57XrFPEyvvPnTTjcjkeihDgbb W3gX8Zc9Ma91nJsac06tPcHNzRlTUky7p1Iw1IpZGE1Xe7HtJM2HNHsnxvRbRfzP9PWg 1l/w== X-Received: by 10.68.217.170 with SMTP id oz10mr29788330pbc.152.1373430405981; Tue, 09 Jul 2013 21:26:45 -0700 (PDT) Received: from localhost ([203.126.243.116]) by mx.google.com with ESMTPSA id fl2sm33652599pab.23.2013.07.09.21.26.43 for (version=TLSv1.1 cipher=RC4-SHA bits=128/128); Tue, 09 Jul 2013 21:26:44 -0700 (PDT) From: peter.crosthwaite@xilinx.com To: peter.maydell@linaro.org Date: Wed, 10 Jul 2013 14:21:42 +1000 Message-Id: <72aae9b8ebbc9a76d2b06faf8666ef8a4b34b92a.1373429432.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.8.3.rc1.44.gb387c77.dirty In-Reply-To: References: X-Gm-Message-State: ALoCoQm6KAm/0ckp/F5eMlBKrYi4UlR9mGL7APMfIfLeFxKxI1F6rrwtFYZGWL6fyQc61dqWwHJI X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.220.53 Cc: qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v1 1/4] target-arm/helper.c: OMAP/StrongARM cp15 crn=0 cleanup X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter Crosthwaite The if block detecting OMAP/StrongARM modifies the id_cp_reginfo .access fields in place. So there is no need to replicate the call to define_arm_cp_reg(). Dropped, and let the OMAP case fall through to the normal behaviour after the in-place modification. Signed-off-by: Peter Crosthwaite --- target-arm/helper.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 5f639fd..47e6c09 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1435,21 +1435,16 @@ void register_cp_regs_for_features(ARMCPU *cpu) arm_feature(env, ARM_FEATURE_STRONGARM)) { ARMCPRegInfo *r; /* Register the blanket "writes ignored" value first to cover the - * whole space. Then define the specific ID registers, but update - * their access field to allow write access, so that they ignore - * writes rather than causing them to UNDEF. + * whole space. Then update the specific ID registers to allow write + * access, so that they ignore writes rather than causing them to + * UNDEF. */ define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { r->access = PL1_RW; - define_one_arm_cp_reg(cpu, r); } - } else { - /* Just register the standard ID registers (read-only, meaning - * that writes will UNDEF). - */ - define_arm_cp_regs(cpu, id_cp_reginfo); } + define_arm_cp_regs(cpu, id_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_AUXCR)) {