From patchwork Fri Jul 5 10:44:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 257095 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 27BEE2C0090 for ; Fri, 5 Jul 2013 20:46:22 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757358Ab3GEKqQ (ORCPT ); Fri, 5 Jul 2013 06:46:16 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:14871 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757343Ab3GEKqP (ORCPT ); Fri, 5 Jul 2013 06:46:15 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Fri, 05 Jul 2013 03:46:09 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 05 Jul 2013 03:45:29 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 05 Jul 2013 03:45:29 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 5 Jul 2013 03:45:52 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 05 Jul 2013 03:45:52 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r65AjE3t022328; Fri, 5 Jul 2013 03:45:50 -0700 (PDT) From: Hiroshi Doyu To: CC: , , , Hiroshi Doyu Subject: [PATCH v2 21/22] iommu/tegra: smmu: Support Multiple ASID Date: Fri, 5 Jul 2013 13:44:56 +0300 Message-ID: <1373021097-32420-22-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Support Multiple Address Space(AS). Tegra SMMU can have multiple ASes. We reserve 2 of them for static assignment, AS[0] for system default, AS[1] for AHB clusters as protected domain from others, where there are many traditional pheripheral devices like USB, SD/MMC. They should be isolated from some smart devices like host1x for system robustness. Even if smart devices behaves wrongly, the traditional devices(SD/MMC, USB) wouldn't be affected, and the system could continue most likely. Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 8a9434e..1945815 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -904,7 +904,18 @@ enum { static int smmu_iommu_add_device(struct device *dev) { int err; - struct dma_iommu_mapping *map = smmu_handle->map[SYSTEM_DEFAULT]; + u64 swgroup; + struct dma_iommu_mapping *map = NULL; + + swgroup = smmu_of_get_memory_client(dev); + switch (swgroup) { + case TEGRA_SWGROUP_BIT(PPCS): + map = smmu_handle->map[SYSTEM_PROTECTED]; + break; + default: + map = smmu_handle->map[SYSTEM_DEFAULT]; + break; + } if (!map) goto out; @@ -915,7 +926,7 @@ static int smmu_iommu_add_device(struct device *dev) return err; } out: - dev_dbg(dev, "Attached to map %p\n", map); + dev_dbg(dev, "Attached to map %p, swgroup:%08llx\n", map, swgroup); return 0; }