From patchwork Fri Jul 5 10:44:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 257093 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 05FEB2C0090 for ; Fri, 5 Jul 2013 20:46:20 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757326Ab3GEKqL (ORCPT ); Fri, 5 Jul 2013 06:46:11 -0400 Received: from hqemgate03.nvidia.com ([216.228.121.140]:17929 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757335Ab3GEKqJ (ORCPT ); Fri, 5 Jul 2013 06:46:09 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 05 Jul 2013 03:53:18 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 05 Jul 2013 03:45:27 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 05 Jul 2013 03:45:27 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Fri, 5 Jul 2013 03:45:50 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 05 Jul 2013 03:45:50 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r65AjE3s022328; Fri, 5 Jul 2013 03:45:49 -0700 (PDT) From: Hiroshi Doyu To: CC: , , , Hiroshi Doyu Subject: [PATCH v2 20/22] iommu/tegra: smmu: Get "nvidia, memory-client" from DT Date: Fri, 5 Jul 2013 13:44:55 +0300 Message-ID: <1373021097-32420-21-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This provides the info about which swgroups a device belongs to. This info is passed from DT. This is necessary for the unified SMMU driver among Tegra SoCs since each has different H/W accelerators. Signed-off-by: Hiroshi Doyu --- .../bindings/iommu/nvidia,tegra30-smmu.txt | 12 ++++++++++++ drivers/iommu/tegra-smmu.c | 20 +++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt index 0c14dca..20ce1fb 100644 --- a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt @@ -11,6 +11,7 @@ Required properties: - nvidia,swgroups: A bitmap of supported HardWare Accelerators(HWA). Each bit represents one swgroup. The assignments may be found in header file . +- nvidia,memory-client: Indicates which swgroups a device belongs to. Example: iommu { @@ -23,3 +24,14 @@ Example: nvidia,swgroups = TEGRA30_SWGROUP_ALL; nvidia,ahb = <&ahb>; }; + + host1x { + compatible = "nvidia,tegra30-host1x", "simple-bus"; + nvidia,memory-client = ; + .... + gr3d { + compatible = "nvidia,tegra30-gr3d"; + nvidia,memory-client = ; + .... + }; diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index ac5d661..8a9434e 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -314,6 +314,24 @@ static inline void smmu_write(struct smmu_device *smmu, u32 val, size_t offs) #define smmu_client_hwgrp(c) (c->as->smmu->swgroup) +static u64 smmu_of_get_memory_client(struct device *dev) +{ + size_t bytes; + const char *propname = "nvidia,memory-client"; + const __be32 *prop; + int i; + u64 swgroup = 0; + + prop = of_get_property(dev->of_node, propname, &bytes); + if (!prop || !bytes) + return 0; + + for (i = 0; i < bytes / sizeof(u32); i++, prop++) + swgroup |= 1ULL << be32_to_cpup(prop); + + return swgroup; +} + static int __smmu_client_set_hwgrp(struct smmu_client *c, u64 map, int on) { @@ -725,7 +743,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain, return -ENOMEM; client->dev = dev; client->as = as; - map = smmu->swgroup; + map = smmu_of_get_memory_client(dev); if (!map) return -EINVAL;