From patchwork Fri Jul 5 10:44:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 257092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E40D02C0090 for ; Fri, 5 Jul 2013 20:46:12 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757337Ab3GEKqJ (ORCPT ); Fri, 5 Jul 2013 06:46:09 -0400 Received: from hqemgate03.nvidia.com ([216.228.121.140]:17928 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750880Ab3GEKqJ (ORCPT ); Fri, 5 Jul 2013 06:46:09 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 05 Jul 2013 03:53:10 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 05 Jul 2013 03:46:46 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 05 Jul 2013 03:46:46 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 5 Jul 2013 03:45:42 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 05 Jul 2013 03:45:42 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r65AjE3n022328; Fri, 5 Jul 2013 03:45:40 -0700 (PDT) From: Hiroshi Doyu To: CC: , , , Hiroshi Doyu Subject: [PATCH v2 15/22] iommu/tegra: smmu: Calculate ASID register offset by ID Date: Fri, 5 Jul 2013 13:44:50 +0300 Message-ID: <1373021097-32420-16-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Calculate ASID register offset by ID so that we can get rid of SoC specific MACROs. This is needed for the unified SMMU driver over Tegra SoCs. Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 35f4a16..95c6c80 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -256,7 +256,7 @@ static const u32 smmu_hwgrp_asid_reg[] = { HWGRP_INIT(VDE), HWGRP_INIT(VI), }; -#define HWGRP_ASID_REG(x) (smmu_hwgrp_asid_reg[x]) +#define HWGRP_ASID_REG(x) ((x) * sizeof(u32) + SMMU_AFI_ASID) /* * Per client for address space