From patchwork Fri Jul 5 10:44:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 257088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BD1FE2C0090 for ; Fri, 5 Jul 2013 20:46:05 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757311Ab3GEKqE (ORCPT ); Fri, 5 Jul 2013 06:46:04 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:14852 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750880Ab3GEKqD (ORCPT ); Fri, 5 Jul 2013 06:46:03 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Fri, 05 Jul 2013 03:45:58 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 05 Jul 2013 03:46:45 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 05 Jul 2013 03:46:45 -0700 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 5 Jul 2013 03:45:40 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 05 Jul 2013 03:45:40 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r65AjE3m022328; Fri, 5 Jul 2013 03:45:39 -0700 (PDT) From: Hiroshi Doyu To: CC: , , , Hiroshi Doyu Subject: [PATCH v2 14/22] iommu/tegra: smmu: Register platform_device to IOMMU dynamically Date: Fri, 5 Jul 2013 13:44:49 +0300 Message-ID: <1373021097-32420-15-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> References: <1373021097-32420-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Register platform_devices to IOMMU dynamically via ops->{add,remove}_device(). Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 1617c90..35f4a16 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -39,6 +39,7 @@ #include #include +#include enum smmu_hwgrp { HWGRP_AFI, @@ -949,6 +950,40 @@ static void smmu_iommu_domain_destroy(struct iommu_domain *domain) dev_dbg(smmu->dev, "smmu_as@%p\n", as); } +/* + * ASID[0] for the system default + * ASID[1] for PPCS, which has SDMMC + * ASID[2][3].. open for drivers, first come, first served. + */ +enum { + SYSTEM_DEFAULT, + SYSTEM_PROTECTED, +}; + +static int smmu_iommu_add_device(struct device *dev) +{ + int err; + struct dma_iommu_mapping *map = smmu_handle->map[SYSTEM_DEFAULT]; + + if (!map) + goto out; + + err = arm_iommu_attach_device(dev, map); + if (err) { + dev_err(dev, "Failed to attach to map %p\n", map); + return err; + } +out: + dev_dbg(dev, "Attached to map %p\n", map); + return 0; +} + +static void smmu_iommu_remove_device(struct device *dev) +{ + dev_dbg(dev, "Detaching from map %p\n", to_dma_iommu_mapping(dev)); + arm_iommu_detach_device(dev); +} + static struct iommu_ops smmu_iommu_ops = { .domain_init = smmu_iommu_domain_init, .domain_destroy = smmu_iommu_domain_destroy, @@ -958,6 +993,8 @@ static struct iommu_ops smmu_iommu_ops = { .unmap = smmu_iommu_unmap, .iova_to_phys = smmu_iommu_iova_to_phys, .domain_has_cap = smmu_iommu_domain_has_cap, + .add_device = smmu_iommu_add_device, + .remove_device = smmu_iommu_remove_device, .pgsize_bitmap = SMMU_IOMMU_PGSIZES, };