Patchwork [v2,05/22] ARM: dt: tegra30: iommu: Add "nvidia,memory-client"

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Submitter Hiroshi Doyu
Date July 5, 2013, 10:44 a.m.
Message ID <1373021097-32420-6-git-send-email-hdoyu@nvidia.com>
Download mbox | patch
Permalink /patch/257087/
State Superseded, archived
Headers show

Comments

Hiroshi Doyu - July 5, 2013, 10:44 a.m.
Add "nvidia,memory-client" to identify which swgroup ID a device
belongs to.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 arch/arm/boot/dts/tegra30.dtsi |   19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
Stephen Warren - July 16, 2013, 11:14 p.m.
On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
> Add "nvidia,memory-client" to identify which swgroup ID a device
> belongs to.

This property also isn't in the documentation.

Again, if client devices are required to have this new property, the DT
isn't backwards-compatible; fail:-(

> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi

> +		nvidia,memory-client = <TEGRA_SWGROUP_HC>;

What if there's more than one SMMU in the system, e.g. since there are
multiple different master-capable buses? Including the SMMU phandle in
the property seems like a good idea so that the SMMU driver knows which
devices are affected by it (although a bus structure with affected
devices under the SMMU represented as nodes under the SMMU DT node seems
a slightly more direct way of representing that, although that solution
does only support systems where bus-master transactions flow up the bus
structure in the same way that CPU transactions flow down it).

What about:

nvidia,smmu = <&smmu TEGRA_SWGROUP_HC>;

?

> @@ -69,6 +75,8 @@
>  			reg = <0x54180000 0x00040000>;
>  			clocks = <&tegra_car 24 &tegra_car 98>;
>  			clock-names = "3d", "3d2";
> +			nvidia,memory-client = <TEGRA_SWGROUP_NV
> +						TEGRA_SWGROUP_NV2>;

Oh, if there can be more than one, I suggest adding "s" to the end of
the property name.
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Hiroshi Doyu - July 29, 2013, 11:06 a.m.
Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 17 Jul 2013 01:14:33 +0200:

> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
> > Add "nvidia,memory-client" to identify which swgroup ID a device
> > belongs to.
> 
> This property also isn't in the documentation.
> 
> Again, if client devices are required to have this new property, the DT
> isn't backwards-compatible; fail:-(

If there's no this property, just falling back to use the system
default address space. I think that this won't break the
compatibility basically. Only problem may be the inconsistency of
setting this property among the HWs in the same group. If one of them
is set in one AS, but not for the other, then the other H/W won't
work. If we really want to have this kind of constraint implmeneted in
DT, some kind of bus model is needed.
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Stephen Warren - July 29, 2013, 5:47 p.m.
On 07/29/2013 05:06 AM, Hiroshi Doyu wrote:
> Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 17 Jul 2013 01:14:33 +0200:
> 
>> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
>>> Add "nvidia,memory-client" to identify which swgroup ID a device
>>> belongs to.
>>
>> This property also isn't in the documentation.
>>
>> Again, if client devices are required to have this new property, the DT
>> isn't backwards-compatible; fail:-(
> 
> If there's no this property, just falling back to use the system
> default address space. I think that this won't break the
> compatibility basically. Only problem may be the inconsistency of
> setting this property among the HWs in the same group.

When you say "group" there, what kind of group? I thought that each HW
module had its own "SWGROUP ID", and hence there are no "HWs in the same
group"?
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Hiroshi Doyu - July 30, 2013, 5:11 a.m.
On Mon, 29 Jul 2013 19:47:04 +0200
Stephen Warren <swarren@wwwdotorg.org> wrote:

> On 07/29/2013 05:06 AM, Hiroshi Doyu wrote:
> > Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 17 Jul 2013 01:14:33 +0200:
> > 
> >> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
> >>> Add "nvidia,memory-client" to identify which swgroup ID a device
> >>> belongs to.
> >>
> >> This property also isn't in the documentation.
> >>
> >> Again, if client devices are required to have this new property, the DT
> >> isn't backwards-compatible; fail:-(
> > 
> > If there's no this property, just falling back to use the system
> > default address space. I think that this won't break the
> > compatibility basically. Only problem may be the inconsistency of
> > setting this property among the HWs in the same group.
> 
> When you say "group" there, what kind of group? I thought that each HW
> module had its own "SWGROUP ID", and hence there are no "HWs in the same
> group"?

A "swgroup" can have multiple HWs. So there are 3 concept here.

swgroup: one client to issue request from MC perspective
HW: swgroup can have multiple HWs(real H/W units)
device driver: Can have multiple swgroups.
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Patch

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 4a9594e..4aa5b4a 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -23,6 +23,7 @@ 
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+		nvidia,memory-client = <TEGRA_SWGROUP_HC>;
 
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -34,6 +35,7 @@ 
 			reg = <0x54040000 0x00040000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_MPE>;
+			nvidia,memory-client = <TEGRA_SWGROUP_MPE>;
 		};
 
 		vi {
@@ -41,6 +43,7 @@ 
 			reg = <0x54080000 0x00040000>;
 			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_VI>;
+			nvidia,memory-client = <TEGRA_SWGROUP_VI>;
 		};
 
 		epp {
@@ -48,6 +51,7 @@ 
 			reg = <0x540c0000 0x00040000>;
 			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_EPP>;
+			nvidia,memory-client = <TEGRA_SWGROUP_EPP>;
 		};
 
 		isp {
@@ -55,6 +59,7 @@ 
 			reg = <0x54100000 0x00040000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_ISP>;
+			nvidia,memory-client = <TEGRA_SWGROUP_ISP>;
 		};
 
 		gr2d {
@@ -62,6 +67,7 @@ 
 			reg = <0x54140000 0x00040000>;
 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
+			nvidia,memory-client = <TEGRA_SWGROUP_G2>;
 		};
 
 		gr3d {
@@ -69,6 +75,8 @@ 
 			reg = <0x54180000 0x00040000>;
 			clocks = <&tegra_car 24 &tegra_car 98>;
 			clock-names = "3d", "3d2";
+			nvidia,memory-client = <TEGRA_SWGROUP_NV
+						TEGRA_SWGROUP_NV2>;
 		};
 
 		dc@54200000 {
@@ -78,6 +86,7 @@ 
 			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp1", "parent";
+			nvidia,memory-client = <TEGRA_SWGROUP_DC>;
 
 			rgb {
 				status = "disabled";
@@ -91,6 +100,7 @@ 
 			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 				 <&tegra_car TEGRA30_CLK_PLL_P>;
 			clock-names = "disp2", "parent";
+			nvidia,memory-client = <TEGRA_SWGROUP_DCB>;
 
 			rgb {
 				status = "disabled";
@@ -247,6 +257,7 @@ 
 		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 8>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -257,6 +268,7 @@ 
 		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 9>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -267,6 +279,7 @@ 
 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 10>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -277,6 +290,7 @@ 
 		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 19>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -287,6 +301,7 @@ 
 		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 		nvidia,dma-request-selector = <&apbdma 20>;
 		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -536,6 +551,7 @@ 
 		reg = <0x78000000 0x200>;
 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -544,6 +560,7 @@ 
 		reg = <0x78000200 0x200>;
 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -552,6 +569,7 @@ 
 		reg = <0x78000400 0x200>;
 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};
 
@@ -560,6 +578,7 @@ 
 		reg = <0x78000600 0x200>;
 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+		nvidia,memory-client = <TEGRA_SWGROUP_PPCS>;
 		status = "disabled";
 	};