Patchwork [v2,03/22] ARM: tegra: Create a DT header defining swgroups ID

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Submitter Hiroshi Doyu
Date July 5, 2013, 10:44 a.m.
Message ID <1373021097-32420-4-git-send-email-hdoyu@nvidia.com>
Download mbox | patch
Permalink /patch/257086/
State Superseded, archived
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Comments

Hiroshi Doyu - July 5, 2013, 10:44 a.m.
Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV.

This will allow the same header to be used by both device tree files,
and drivers implementing this binding, which guarantees that the two
stay in sync. This also makes device trees more readable by using names
instead of magic numbers.

Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
---
 include/dt-bindings/memory/tegra-swgroup.h |   50 ++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 include/dt-bindings/memory/tegra-swgroup.h
Stephen Warren - July 16, 2013, 11:07 p.m.
On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
> Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
> binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV.
> 
> This will allow the same header to be used by both device tree files,
> and drivers implementing this binding, which guarantees that the two
> stay in sync. This also makes device trees more readable by using names
> instead of magic numbers.

Why does the driver need these constants; shouldn't it simply support
0..n SW group IDs that all work the same way? Or, is there some reason
for it to know the identities?

> diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h

s/memory/iommu/?

s/tegra-swgroup.h/tegra-smmu.h/?

> +#define TEGRA_SWGROUP_AFI 0

Should this file document which values are valid for which SoCs? Should
there be separate files for each SoC; I don't know if it's guaranteed
that IDs won't be re-assigned between different SoCs.

> +#define TEGRA_SWGROUP_BIT(x)	(1ULL << TEGRA_SWGROUP_##x)
> +
> +#define TEGRA30_SWGROUP_ALL	<0x00000000 0x000779ff>
> +#define TEGRA114_SWGROUP_ALL	<0x00000000 0x01b659fe>

Are those 3 values needed by DT files, or just the driver?
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Hiroshi Doyu - July 29, 2013, 10:53 a.m.
Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 17 Jul 2013 01:07:12 +0200:

> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
> > Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
> > binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV.
> > 
> > This will allow the same header to be used by both device tree files,
> > and drivers implementing this binding, which guarantees that the two
> > stay in sync. This also makes device trees more readable by using names
> > instead of magic numbers.
> 
> Why does the driver need these constants; shouldn't it simply support
> 0..n SW group IDs that all work the same way? Or, is there some reason
> for it to know the identities?
> 
> > diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h
> 
> s/memory/iommu/?

This info would be used in PMC code as well, which H/W belongs to
which swgroup. So I use the term "memory(-client)" instead of "iommu".

> s/tegra-swgroup.h/tegra-smmu.h/?

Is "tegra-memory-clients.h" preferable, then?

> > +#define TEGRA_SWGROUP_AFI 0
> 
> Should this file document which values are valid for which SoCs? Should
> there be separate files for each SoC; I don't know if it's guaranteed
> that IDs won't be re-assigned between different SoCs.

I've checked all SoC which I can refer. Those IDs are calculated from
the register offset. But I haven't got any explicit guarantee from H/W
designers yet.

> > +#define TEGRA_SWGROUP_BIT(x)	(1ULL << TEGRA_SWGROUP_##x)
> > +
> > +#define TEGRA30_SWGROUP_ALL	<0x00000000 0x000779ff>
> > +#define TEGRA114_SWGROUP_ALL	<0x00000000 0x01b659fe>
> 
> Are those 3 values needed by DT files, or just the driver?

Only from DT.
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Stephen Warren - July 29, 2013, 5:45 p.m.
On 07/29/2013 04:53 AM, Hiroshi Doyu wrote:
> Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 17 Jul 2013 01:07:12 +0200:
> 
>> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
>>> Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
>>> binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV.
>>>
>>> This will allow the same header to be used by both device tree files,
>>> and drivers implementing this binding, which guarantees that the two
>>> stay in sync. This also makes device trees more readable by using names
>>> instead of magic numbers.
>>
>> Why does the driver need these constants; shouldn't it simply support
>> 0..n SW group IDs that all work the same way? Or, is there some reason
>> for it to know the identities?
>>
>>> diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h
>>
>> s/memory/iommu/?
> 
> This info would be used in PMC code as well, which H/W belongs to
> which swgroup. So I use the term "memory(-client)" instead of "iommu".

Why does the PMC care? An explanation of exactly what SW needs to know
about these groups and why would be a good idea.

>> s/tegra-swgroup.h/tegra-smmu.h/?
> 
> Is "tegra-memory-clients.h" preferable, then?

Perhaps, although aren't these IDs specific to the connection between
modules and the SMMU? Or, are these IDs some more global concept; the HW
modules in question pass the same IDs to both the SMMU and to other HW
modules for some reason?

>>> +#define TEGRA_SWGROUP_BIT(x)	(1ULL << TEGRA_SWGROUP_##x)
>>> +
>>> +#define TEGRA30_SWGROUP_ALL	<0x00000000 0x000779ff>
>>> +#define TEGRA114_SWGROUP_ALL	<0x00000000 0x01b659fe>
>>
>> Are those 3 values needed by DT files, or just the driver?
> 
> Only from DT.

If the values are only needed to write the DT content, I'd tend to
prefer not defining them in a header in <dt-bindings/>; I consider that
directory a definition of the constants that define the ABI itself, not
as a random place to put useful things for DT. You can include headers
in the *.dts directory itself.

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Hiroshi Doyu - July 30, 2013, 4:56 a.m.
On Mon, 29 Jul 2013 19:45:15 +0200
Stephen Warren <swarren@wwwdotorg.org> wrote:

> On 07/29/2013 04:53 AM, Hiroshi Doyu wrote:
> > Stephen Warren <swarren@wwwdotorg.org> wrote @ Wed, 17 Jul 2013 01:07:12 +0200:
> > 
> >> On 07/05/2013 04:44 AM, Hiroshi Doyu wrote:
> >>> Create a header file to define the swgroup IDs used by the IOMMU(SMMU)
> >>> binding. "swgroup" is a group of H/W clients in Tegra SoC from S/W POV.
> >>>
> >>> This will allow the same header to be used by both device tree files,
> >>> and drivers implementing this binding, which guarantees that the two
> >>> stay in sync. This also makes device trees more readable by using names
> >>> instead of magic numbers.
> >>
> >> Why does the driver need these constants; shouldn't it simply support
> >> 0..n SW group IDs that all work the same way? Or, is there some reason
> >> for it to know the identities?
> >>
> >>> diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h
> >>
> >> s/memory/iommu/?
> > 
> > This info would be used in PMC code as well, which H/W belongs to
> > which swgroup. So I use the term "memory(-client)" instead of "iommu".
> 
> Why does the PMC care? An explanation of exactly what SW needs to know
> about these groups and why would be a good idea.

Joseph, can you explain a bit here?
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Patch

diff --git a/include/dt-bindings/memory/tegra-swgroup.h b/include/dt-bindings/memory/tegra-swgroup.h
new file mode 100644
index 0000000..4cfa769
--- /dev/null
+++ b/include/dt-bindings/memory/tegra-swgroup.h
@@ -0,0 +1,50 @@ 
+/*
+ * This header provides constants for binding nvidia,swgroup ID
+ */
+
+#ifndef _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H
+#define _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H
+
+#define TEGRA_SWGROUP_AFI 0
+#define TEGRA_SWGROUP_AVPC 1
+#define TEGRA_SWGROUP_DC 2
+#define TEGRA_SWGROUP_DCB 3
+#define TEGRA_SWGROUP_EPP 4
+#define TEGRA_SWGROUP_G2 5
+#define TEGRA_SWGROUP_HC 6
+#define TEGRA_SWGROUP_HDA 7
+#define TEGRA_SWGROUP_ISP 8
+#define TEGRA_SWGROUP_ISP2 SWGID_ISP
+/* UNUSED: 9 */
+/* UNUSED: 10 */
+#define TEGRA_SWGROUP_MPE 11
+#define TEGRA_SWGROUP_MSENC SWGID_MPE
+#define TEGRA_SWGROUP_NV 12
+#define TEGRA_SWGROUP_NV2 13
+#define TEGRA_SWGROUP_PPCS 14
+#define TEGRA_SWGROUP_SATA2 15
+#define TEGRA_SWGROUP_SATA 16
+#define TEGRA_SWGROUP_VDE 17
+#define TEGRA_SWGROUP_VI 18
+#define TEGRA_SWGROUP_VIC 19
+#define TEGRA_SWGROUP_XUSB_HOST 20
+#define TEGRA_SWGROUP_XUSB_DEV 21
+#define TEGRA_SWGROUP_A9AVP 22
+#define TEGRA_SWGROUP_TSEC 23
+#define TEGRA_SWGROUP_PPCS1 24
+/* UNUSED: 25 */
+/* UNUSED: 26 */
+/* UNUSED: 27 */
+/* UNUSED: 28 */
+/* UNUSED: 29 */
+/* UNUSED: 30 */
+/* UNUSED: 31 */
+
+/* Reserved: 32-63 */
+
+#define TEGRA_SWGROUP_BIT(x)	(1ULL << TEGRA_SWGROUP_##x)
+
+#define TEGRA30_SWGROUP_ALL	<0x00000000 0x000779ff>
+#define TEGRA114_SWGROUP_ALL	<0x00000000 0x01b659fe>
+
+#endif /* _DT_BINDINGS_MEMORY_TEGRA_SWGROUP_H */