| Message ID | 1372970462-10338-1-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show
Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7978E2C0096 for <incoming@patchwork.ozlabs.org>; Fri, 5 Jul 2013 06:41:40 +1000 (EST) Received: from localhost ([::1]:50236 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>) id 1UuqLR-0004P9-3l for incoming@patchwork.ozlabs.org; Thu, 04 Jul 2013 16:41:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from <rth7680@gmail.com>) id 1UuqL1-0004OA-Sq for qemu-devel@nongnu.org; Thu, 04 Jul 2013 16:41:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from <rth7680@gmail.com>) id 1UuqKz-0002IR-91 for qemu-devel@nongnu.org; Thu, 04 Jul 2013 16:41:11 -0400 Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:38718) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from <rth7680@gmail.com>) id 1UuqKz-0002IJ-3T for qemu-devel@nongnu.org; Thu, 04 Jul 2013 16:41:09 -0400 Received: by mail-pa0-f43.google.com with SMTP id hz11so1594199pad.2 for <qemu-devel@nongnu.org>; Thu, 04 Jul 2013 13:41:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; bh=/AyJjNLwrh6JC/xSdFOIyKRgTe9lDBMj/ogYcxoTGeA=; b=L44FU0DcnpPbh2VB8Ol2jz3DZ/82IkZxJdyWenLON/aYedMfTW+VzmTZomVgbrpDkX e6kZg2q/NWjdSySCfSiTJ8RzJZFTPGaBZsXKGgVDsrIgK9L83VwBOV4oDLLaVX0/pk/3 eVXwe3lf8YSJLZyUL7bFUmbmp1nqE2+NUevPc7tZeF+tEXwF0F+Hil/IEyJ1l0DQ3/gy I9uGj5ZkgpltfTx/5NN26pkB62UDgH3Hbv5MVQk2lSK+4SldF8lNAmSTBilVV8NDVQPA LNvriV1Hle4McQdQqrANyp71ihBQDGqH4GG+/H0WKAUAD8yHuA+AKeGJMRgIutWBNb9h k33A== X-Received: by 10.68.171.196 with SMTP id aw4mr7010419pbc.78.1372970467622; Thu, 04 Jul 2013 13:41:07 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id pb5sm4093184pbc.29.2013.07.04.13.41.05 for <multiple recipients> (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 04 Jul 2013 13:41:06 -0700 (PDT) From: Richard Henderson <rth@twiddle.net> To: qemu-devel@nongnu.org Date: Thu, 4 Jul 2013 13:40:47 -0700 Message-Id: <1372970462-10338-1-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::22b Cc: peter.maydell@linaro.org, aliguori@us.ibm.com Subject: [Qemu-devel] [PATCH v4 00/15] tcg: remainder and tcg-arm updates X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org |
Changes v3-v4: * Feedback from Peter Maydell: + Use only HWCAP_ARM_IDIVA to detect division + New patch 9 to rename variable from armv5 to armv5t + Adjust ARM ISA logic patch for identifying armv5t I didn't go whole hog wrt detecting armv5t w/ hwcap, as I didn't really want to have to test that somehow. It'll just fall back to the v4 version if preprocessor defines aren't present, or we know we're on v6 or later. r~ The following changes since commit ab8bf29078e0ab8347e2ff8b4e5542f7a0c751cf: Merge remote-tracking branch 'qemu-kvm/uq/master' into staging (2013-07-03 08:37:00 -0500) are available in the git repository at: git://github.com/rth7680/qemu.git tcg-next for you to fetch changes up to e17b0b19e60d792581addd828fd9196dc5edc882: tcg-arm: Implement tcg_register_jit (2013-07-04 13:06:16 -0700) ---------------------------------------------------------------- Richard Henderson (15): tcg: Add myself to general TCG maintainership tcg: Split rem requirement from div requirement tcg-arm: Don't implement rem tcg-ppc: Don't implement rem tcg-ppc64: Don't implement rem tcg: Allow non-constant control macros tcg: Simplify logic using TCG_OPF_NOT_PRESENT tcg-arm: Make use of conditional availability of opcodes for divide tcg-arm: Rename use_armv5_instructions to use_armvt5_instructions tcg-arm: Simplify logic in detecting the ARM ISA in use tcg-arm: Use AT_PLATFORM to detect the host ISA tcg: Fix high_pc fields in .debug_info tcg: Move the CIE and FDE header definitions to common code tcg-i386: Use QEMU_BUILD_BUG_ON instead of assert for frame size tcg-arm: Implement tcg_register_jit MAINTAINERS | 1 + tcg/aarch64/tcg-target.h | 2 + tcg/arm/tcg-target.c | 178 ++++++++++++++++++++++++++++++----------------- tcg/arm/tcg-target.h | 15 ++-- tcg/hppa/tcg-target.c | 35 +++------- tcg/hppa/tcg-target.h | 1 + tcg/i386/tcg-target.c | 45 +++++------- tcg/ia64/tcg-target.h | 2 + tcg/mips/tcg-target.h | 1 + tcg/ppc/tcg-target.c | 14 ---- tcg/ppc/tcg-target.h | 1 + tcg/ppc64/tcg-target.c | 26 ------- tcg/ppc64/tcg-target.h | 2 + tcg/sparc/tcg-target.c | 35 +++------- tcg/sparc/tcg-target.h | 2 + tcg/tcg-op.h | 32 +++++++-- tcg/tcg-opc.h | 36 +++++----- tcg/tcg.c | 26 +++++-- tcg/tcg.h | 6 +- tcg/tci/tcg-target.h | 6 +- 20 files changed, 248 insertions(+), 218 deletions(-)