Patchwork [-V2] powerpc/mm: Use the correct SLB(LLP) encoding in tlbie instruction

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Submitter Aneesh Kumar K.V
Date July 4, 2013, 5:04 a.m.
Message ID <1372914285-30562-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
Download mbox | patch
Permalink /patch/256792/
State Accepted
Commit de640959b63ad437c21f2a217f25332c4ea863cb
Headers show

Comments

Aneesh Kumar K.V - July 4, 2013, 5:04 a.m.
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>

The sllp value is stored in mmu_psize_defs in such a way that we can easily OR
the value to get the operand for slbmte instruction. ie, the L and LP bits are
not contiguous. Decode the bits and use them correctly in tlbie.
regression is introduced by 1f6aaaccb1b3af8613fe45781c1aefee2ae8c6b3
"powerpc: Update tlbie/tlbiel as per ISA doc"

Reported-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
Changes from V1:
* use #define constants instead of opencoded values

 arch/powerpc/mm/hash_native_64.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)
Aneesh Kumar K.V - July 23, 2013, 1:50 a.m.
"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> writes:

> From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
>
> The sllp value is stored in mmu_psize_defs in such a way that we can easily OR
> the value to get the operand for slbmte instruction. ie, the L and LP bits are
> not contiguous. Decode the bits and use them correctly in tlbie.
> regression is introduced by 1f6aaaccb1b3af8613fe45781c1aefee2ae8c6b3
> "powerpc: Update tlbie/tlbiel as per ISA doc"
>
> Reported-by: Paul Mackerras <paulus@samba.org>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> Changes from V1:
> * use #define constants instead of opencoded values
>
>  arch/powerpc/mm/hash_native_64.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
> index 0530ff7..c33d939 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -43,6 +43,7 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
>  {
>  	unsigned long va;
>  	unsigned int penc;
> +	unsigned long sllp;
>
>  	/*
>  	 * We need 14 to 65 bits of va for a tlibe of 4K page
> @@ -64,7 +65,9 @@ static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
>  		/* clear out bits after (52) [0....52.....63] */
>  		va &= ~((1ul << (64 - 52)) - 1);
>  		va |= ssize << 8;
> -		va |= mmu_psize_defs[apsize].sllp << 6;
> +		sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) |
> +			((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
> +		va |= sllp << 5;
>  		asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
>  			     : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
>  			     : "memory");
> @@ -98,6 +101,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
>  {
>  	unsigned long va;
>  	unsigned int penc;
> +	unsigned long sllp;
>
>  	/* VPN_SHIFT can be atmost 12 */
>  	va = vpn << VPN_SHIFT;
> @@ -113,7 +117,9 @@ static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
>  		/* clear out bits after(52) [0....52.....63] */
>  		va &= ~((1ul << (64 - 52)) - 1);
>  		va |= ssize << 8;
> -		va |= mmu_psize_defs[apsize].sllp << 6;
> +		sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) |
> +			((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
> +		va |= sllp << 5;
>  		asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
>  			     : : "r"(va) : "memory");
>  		break;


Any update on this ?

-aneesh

Patch

diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 0530ff7..c33d939 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -43,6 +43,7 @@  static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
 {
 	unsigned long va;
 	unsigned int penc;
+	unsigned long sllp;
 
 	/*
 	 * We need 14 to 65 bits of va for a tlibe of 4K page
@@ -64,7 +65,9 @@  static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
 		/* clear out bits after (52) [0....52.....63] */
 		va &= ~((1ul << (64 - 52)) - 1);
 		va |= ssize << 8;
-		va |= mmu_psize_defs[apsize].sllp << 6;
+		sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) |
+			((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
+		va |= sllp << 5;
 		asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
 			     : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
 			     : "memory");
@@ -98,6 +101,7 @@  static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
 {
 	unsigned long va;
 	unsigned int penc;
+	unsigned long sllp;
 
 	/* VPN_SHIFT can be atmost 12 */
 	va = vpn << VPN_SHIFT;
@@ -113,7 +117,9 @@  static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
 		/* clear out bits after(52) [0....52.....63] */
 		va &= ~((1ul << (64 - 52)) - 1);
 		va |= ssize << 8;
-		va |= mmu_psize_defs[apsize].sllp << 6;
+		sllp = ((mmu_psize_defs[apsize].sllp & SLB_VSID_L) >> 6) |
+			((mmu_psize_defs[apsize].sllp & SLB_VSID_LP) >> 4);
+		va |= sllp << 5;
 		asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
 			     : : "r"(va) : "memory");
 		break;