From patchwork Wed Jul 3 21:29:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 256759 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A63302C00A3 for ; Thu, 4 Jul 2013 07:37:35 +1000 (EST) Received: from localhost ([::1]:35701 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UuUiA-0002JR-2R for incoming@patchwork.ozlabs.org; Wed, 03 Jul 2013 17:35:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50607) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UuUcn-00035d-39 for qemu-devel@nongnu.org; Wed, 03 Jul 2013 17:30:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UuUck-0005kG-C2 for qemu-devel@nongnu.org; Wed, 03 Jul 2013 17:30:04 -0400 Received: from mail-pa0-x233.google.com ([2607:f8b0:400e:c03::233]:50991) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UuUcj-0005hE-Su for qemu-devel@nongnu.org; Wed, 03 Jul 2013 17:30:02 -0400 Received: by mail-pa0-f51.google.com with SMTP id lf11so642764pab.10 for ; Wed, 03 Jul 2013 14:30:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=uY7vyGRyrU0KI8+TMXq57IpM4J3/KrYSXckWFwMhmX8=; b=XmPcez6qvWEIArSBEct5HQ3uArfKTgiq55BelnQfP7joiejHjoE8VUm3iuKFwDdWwy 9w8bF0dIeCpjj6Ro6PkXpOl9SRUmrfWFCqXjy8VpTM6Fn51oi1Acejq+aS31oBBtr81a oNMZLPNKW3FYkNiy50HpX8iUJBVkol5ArMfAZiPHzNRKSM5KHYs8kXzCqyXkv4tlrRQD mPfECBpOByU9o6+/4aL2pDPC0BuvxQ8bpA2YPyHLebe9O1qDBRX5Kpd/0PmqPsJmnitW cPtb3naS9gTbX9+71ob4t67UAjxp7bhXmeDzm2FdbAiVatgnkLABvqVV2q0ZdrCeerjI dipA== X-Received: by 10.68.195.35 with SMTP id ib3mr2626169pbc.53.1372887001050; Wed, 03 Jul 2013 14:30:01 -0700 (PDT) Received: from fremont.twiddle.net (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPSA id s5sm13109431pbo.38.2013.07.03.14.29.57 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 03 Jul 2013 14:30:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 3 Jul 2013 14:29:22 -0700 Message-Id: <1372886968-17497-9-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1372886968-17497-1-git-send-email-rth@twiddle.net> References: <1372886968-17497-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2607:f8b0:400e:c03::233 Cc: aliguori@us.ibm.com, claudio.fontana@huawei.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH v3 08/14] tcg-arm: Make use of conditional availability of opcodes for divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org We can now detect and use divide instructions at runtime, rather than having to restrict their availability to compile-time. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 16 ++++++++++++++-- tcg/arm/tcg-target.h | 14 ++++++++------ 2 files changed, 22 insertions(+), 8 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 8321f80..2c46ceb 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0; #endif #undef USE_ARMV7_INSTRUCTIONS +#ifndef use_idiv_instructions +bool use_idiv_instructions; +#endif +#ifdef CONFIG_GETAUXVAL +# include +#endif + #ifndef NDEBUG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "%r0", @@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, -#if TCG_TARGET_HAS_div_i32 { INDEX_op_div_i32, { "r", "r", "r" } }, { INDEX_op_divu_i32, { "r", "r", "r" } }, -#endif { -1 }, }; static void tcg_target_init(TCGContext *s) { +#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions) + { + unsigned long hwcap = getauxval(AT_HWCAP); + use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT); + } +#endif + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, (1 << TCG_REG_R0) | diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 263ea03..5cd9d6a 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -49,6 +49,13 @@ typedef enum { #define TCG_TARGET_NB_REGS 16 +#ifdef __ARM_ARCH_EXT_IDIV__ +#define use_idiv_instructions 1 +#else +extern bool use_idiv_instructions; +#endif + + /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R13 #define TCG_TARGET_STACK_ALIGN 8 @@ -73,12 +80,7 @@ typedef enum { #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_muls2_i32 1 - -#ifdef __ARM_ARCH_EXT_IDIV__ -#define TCG_TARGET_HAS_div_i32 1 -#else -#define TCG_TARGET_HAS_div_i32 0 -#endif +#define TCG_TARGET_HAS_div_i32 use_idiv_instructions #define TCG_TARGET_HAS_rem_i32 0 extern bool tcg_target_deposit_valid(int ofs, int len);