Patchwork [rs6000] PR target/57150, do not use VSX instructions for long double caller saves

login
register
mail settings
Submitter Joseph S. Myers
Date July 3, 2013, 4:09 p.m.
Message ID <Pine.LNX.4.64.1307031608490.18167@digraph.polyomino.org.uk>
Download mbox | patch
Permalink /patch/256699/
State New
Headers show

Comments

Joseph S. Myers - July 3, 2013, 4:09 p.m.
On Fri, 3 May 2013, Michael Meissner wrote:

> 2013-05-03  Michael Meissner  <meissner@linux.vnet.ibm.com>
> 
> 	PR target/57150
> 	* config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Use DFmode
> 	to save TFmode registers and DImode to save TImode registers for
> 	caller save operations.
> 	(HARD_REGNO_CALL_PART_CLOBBERED): TFmode and TDmode do not need to
> 	mark being partially clobbered since they only use the first
> 	double word.
> 
> 	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): TFmode
> 	and TDmode only use the upper 64-bits of each VSX register.

That change has the effect that reload thinks TFmode (and no doubt
TDmode) only takes two registers even when in general registers,
causing a segfault in glibc's test-ldouble built for soft float.

I'm testing this patch (this diff is against 4.8 branch) to fix this;
at least, it fixes the glibc testing issue.  Since the original patch
went on 4.7 and 4.8 branches as well as trunk, I propose this patch
for the branches as well as trunk.  You may wish to test it in your
original VSX configuration.

2013-07-03  Joseph Myers  <joseph@codesourcery.com>

	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Only
	adjust register size for TDmode and TFmode for VSX registers.
David Edelsohn - July 9, 2013, 10 p.m.
On Wed, Jul 3, 2013 at 12:09 PM, Joseph S. Myers
<joseph@codesourcery.com> wrote:
> On Fri, 3 May 2013, Michael Meissner wrote:
>
>> 2013-05-03  Michael Meissner  <meissner@linux.vnet.ibm.com>
>>
>>       PR target/57150
>>       * config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Use DFmode
>>       to save TFmode registers and DImode to save TImode registers for
>>       caller save operations.
>>       (HARD_REGNO_CALL_PART_CLOBBERED): TFmode and TDmode do not need to
>>       mark being partially clobbered since they only use the first
>>       double word.
>>
>>       * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): TFmode
>>       and TDmode only use the upper 64-bits of each VSX register.
>
> That change has the effect that reload thinks TFmode (and no doubt
> TDmode) only takes two registers even when in general registers,
> causing a segfault in glibc's test-ldouble built for soft float.
>
> I'm testing this patch (this diff is against 4.8 branch) to fix this;
> at least, it fixes the glibc testing issue.  Since the original patch
> went on 4.7 and 4.8 branches as well as trunk, I propose this patch
> for the branches as well as trunk.  You may wish to test it in your
> original VSX configuration.
>
> 2013-07-03  Joseph Myers  <joseph@codesourcery.com>
>
>         * config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Only
>         adjust register size for TDmode and TFmode for VSX registers.

I thought that you already were applying it, not asking for approval.
The patch is okay.

TFmode and TImode on VSX need some TLC.

- David
Michael Meissner - July 15, 2013, 10:45 p.m.
On Wed, Jul 03, 2013 at 04:09:53PM +0000, Joseph S. Myers wrote:
> On Fri, 3 May 2013, Michael Meissner wrote:
> 
> > 2013-05-03  Michael Meissner  <meissner@linux.vnet.ibm.com>
> > 
> > 	PR target/57150
> > 	* config/rs6000/rs6000.h (HARD_REGNO_CALLER_SAVE_MODE): Use DFmode
> > 	to save TFmode registers and DImode to save TImode registers for
> > 	caller save operations.
> > 	(HARD_REGNO_CALL_PART_CLOBBERED): TFmode and TDmode do not need to
> > 	mark being partially clobbered since they only use the first
> > 	double word.
> > 
> > 	* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): TFmode
> > 	and TDmode only use the upper 64-bits of each VSX register.
> 
> That change has the effect that reload thinks TFmode (and no doubt
> TDmode) only takes two registers even when in general registers,
> causing a segfault in glibc's test-ldouble built for soft float.

Sorry about that.  Thanks for catching it.

Patch

Index: config/rs6000/rs6000.c
===================================================================
--- config/rs6000/rs6000.c	(revision 200641)
+++ config/rs6000/rs6000.c	(working copy)
@@ -2190,7 +2190,8 @@  rs6000_init_hard_regno_mode_ok (bool global_init_p
 	  int reg_size2 = reg_size;
 
 	  /* TFmode/TDmode always takes 2 registers, even in VSX.  */
-	  if (m == TDmode || m == TFmode)
+	  if (TARGET_VSX && VSX_REG_CLASS_P (c)
+	      && (m == TDmode || m == TFmode))
 	    reg_size2 = UNITS_PER_FP_WORD;
 
 	  rs6000_class_max_nregs[m][c]