| Message ID | 1239050219-4477-1-git-send-email-galak@kernel.crashing.org (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | 7281f5dc2c9582f3efaed9b367837ca6117d7b7f |
| Delegated to: | Kumar Gala |
| Headers | show |
On Mon, 2009-04-06 at 15:36 -0500, Kumar Gala wrote: > The tlbilx opcode was not matching the Power ISA 2.06 arch spec. > The old opcode was an early suggested opcode that changed during the > 2.06 architecture process. [snip] > #define PPC_INST_STSWI 0x7c0005aa > #define PPC_INST_STSWX 0x7c00052a > -#define PPC_INST_TLBILX 0x7c000626 > +#define PPC_INST_TLBILX 0x7c000024 > #define PPC_INST_WAIT 0x7c00007c How do you want to handle the current binutils code that implements tlbilx and its extended mnemonics? Should they be changed to use secondary opcode 18 instead of 787 as per the ISA 2.06 doc? {"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}}, {"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}}, {"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, PPCNONE, {0}}, {"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}}, If you want to change the tlbilx entry to use 18 rather than 787, let me know whether you want me to make the change or whether you (Edmar?) will handle it. I'll note the extended mnemonics should be moved before tlbilx so that the disassembler will use them (if appropriate) instead of the base instruction. Peter
On Apr 7, 2009, at 12:36 PM, Peter Bergner wrote: > On Mon, 2009-04-06 at 15:36 -0500, Kumar Gala wrote: >> The tlbilx opcode was not matching the Power ISA 2.06 arch spec. >> The old opcode was an early suggested opcode that changed during the >> 2.06 architecture process. > [snip] >> #define PPC_INST_STSWI 0x7c0005aa >> #define PPC_INST_STSWX 0x7c00052a >> -#define PPC_INST_TLBILX 0x7c000626 >> +#define PPC_INST_TLBILX 0x7c000024 >> #define PPC_INST_WAIT 0x7c00007c > > How do you want to handle the current binutils code that implements > tlbilx > and its extended mnemonics? Should they be changed to use secondary > opcode > 18 instead of 787 as per the ISA 2.06 doc? YES ! :) > {"tlbilx", X(31,787), X_MASK, E500MC, > PPCNONE, {T, RA0, RB}}, > {"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, > PPCNONE, {0}}, > {"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, > PPCNONE, {0}}, > {"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, > PPCNONE, {RA0, RB}}, > > If you want to change the tlbilx entry to use 18 rather than 787, > let me > know whether you want me to make the change or whether you (Edmar?) > will > handle it. > > I'll note the extended mnemonics should be moved before tlbilx so > that the > disassembler will use them (if appropriate) instead of the base > instruction. I'll check w/Edmar. - k
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index f4a4db8..640ccbb 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -43,7 +43,7 @@ #define PPC_INST_STSWI 0x7c0005aa #define PPC_INST_STSWX 0x7c00052a -#define PPC_INST_TLBILX 0x7c000626 +#define PPC_INST_TLBILX 0x7c000024 #define PPC_INST_WAIT 0x7c00007c /* macros to insert fields into opcodes */
The tlbilx opcode was not matching the Power ISA 2.06 arch spec. The old opcode was an early suggested opcode that changed during the 2.06 architecture process. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> --- arch/powerpc/include/asm/ppc-opcode.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)