From patchwork Mon Jul 1 14:16:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chin Liang See X-Patchwork-Id: 256148 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C76202C0090 for ; Tue, 2 Jul 2013 00:16:52 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0045D4A1EB; Mon, 1 Jul 2013 16:16:50 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BApP2b9uYxWo; Mon, 1 Jul 2013 16:16:50 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0DEBE4A1FB; Mon, 1 Jul 2013 16:16:49 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EC8DA4A1FB for ; Mon, 1 Jul 2013 16:16:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K+pzN4Qti8eq for ; Mon, 1 Jul 2013 16:16:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 BL_NJABL=ERR(-1.5) (only DNSBL check requested) Received: from co9outboundpool.messaging.microsoft.com (co9ehsobe005.messaging.microsoft.com [207.46.163.28]) by theia.denx.de (Postfix) with ESMTPS id 60C8A4A1EB for ; Mon, 1 Jul 2013 16:16:29 +0200 (CEST) Received: from mail177-co9-R.bigfish.com (10.236.132.245) by CO9EHSOBE010.bigfish.com (10.236.130.73) with Microsoft SMTP Server id 14.1.225.23; Mon, 1 Jul 2013 14:16:26 +0000 Received: from mail177-co9 (localhost [127.0.0.1]) by mail177-co9-R.bigfish.com (Postfix) with ESMTP id 5264FBE010E; Mon, 1 Jul 2013 14:16:26 +0000 (UTC) X-Forefront-Antispam-Report: CIP:66.35.236.232; KIP:(null); UIP:(null); IPV:NLI; H:SJ-ITEXEDGE02.altera.priv.altera.com; RD:none; EFVD:NLI X-SpamScore: 2 X-BigFish: VS2(zz8d0Ic8kzz1f42h1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6hzz17326ah8275bh8275dhz2fh2a8h668h839h93fhd24hf0ah107ah1288h12a5h12a9h12bdh137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1d0ch1d2eh1d3fh1dfeh1dffh1e1dh1e23h1155h) Received-SPF: pass (mail177-co9: domain of altera.com designates 66.35.236.232 as permitted sender) client-ip=66.35.236.232; envelope-from=clsee@altera.com; helo=SJ-ITEXEDGE02.altera.priv.altera.com ; v.altera.com ; Received: from mail177-co9 (localhost.localdomain [127.0.0.1]) by mail177-co9 (MessageSwitch) id 1372688184439031_4725; Mon, 1 Jul 2013 14:16:24 +0000 (UTC) Received: from CO9EHSMHS007.bigfish.com (unknown [10.236.132.247]) by mail177-co9.bigfish.com (Postfix) with ESMTP id 5DBAF780081; Mon, 1 Jul 2013 14:16:24 +0000 (UTC) Received: from SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) by CO9EHSMHS007.bigfish.com (10.236.130.17) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 1 Jul 2013 14:16:24 +0000 Received: from sj-mail01.altera.com (137.57.1.6) by SJ-ITEXEDGE02.altera.priv.altera.com (66.35.236.232) with Microsoft SMTP Server id 8.3.298.1; Mon, 1 Jul 2013 07:06:04 -0700 Received: from drezykow-VirtualBox (tx-clsee-530.altera.priv.altera.com [137.57.188.103]) by sj-mail01.altera.com (8.13.7+Sun/8.13.7) with SMTP id r61EGL69021904; Mon, 1 Jul 2013 07:16:21 -0700 (PDT) Received: by drezykow-VirtualBox (sSMTP sendmail emulation); Mon, 01 Jul 2013 09:16:14 -0500 Message-ID: <1372688174.12363.9.camel@drezykow-VirtualBox.altera.com> From: Chin Liang See To: ZY - pavel Date: Mon, 1 Jul 2013 09:16:14 -0500 In-Reply-To: <20130701104615.GC26322@amd.pavel.ucw.cz> References: <0BB3B561D7068A4E89FD8E9ABFB538BEB3B2E44331@PG-ITMSG03.altera.priv.altera.com> <20130628114423.GE22234@amd.pavel.ucw.cz> <1372436557.3106.16.camel@drezykow-VirtualBox.altera.com> <20130701104615.GC26322@amd.pavel.ucw.cz> X-Mailer: Evolution 3.2.3-0ubuntu6 MIME-Version: 1.0 X-OriginatorOrg: altera.com Cc: ZY - u-boot , Chin Liang See , ZY@theia.denx.de, ZY - sr Subject: [U-Boot] [PATCH v2 1/1] socfpga: Creating driver for Reset Manager X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de socfpga: Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See --- arch/arm/cpu/armv7/socfpga/Makefile | 2 +- arch/arm/cpu/armv7/socfpga/misc.c | 27 ----------- arch/arm/cpu/armv7/socfpga/reset_manager.c | 52 +++++++++++++++++++++ arch/arm/include/asm/arch-socfpga/reset_manager.h | 10 ++-- 4 files changed, 60 insertions(+), 31 deletions(-) create mode 100644 arch/arm/cpu/armv7/socfpga/reset_manager.c diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile index 376a4bd..518e67a 100644 --- a/arch/arm/cpu/armv7/socfpga/Makefile +++ b/arch/arm/cpu/armv7/socfpga/Makefile @@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS-y := misc.o timer.o +COBJS-y := misc.o timer.o reset_manager.o COBJS-$(CONFIG_SPL_BUILD) += spl.o COBJS := $(COBJS-y) diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index fa16424..59f5b94 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -17,36 +17,9 @@ #include #include -#include DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_reset_manager *reset_manager_base = - (void *)SOCFPGA_RSTMGR_ADDRESS; - -/* - * Write the reset manager register to cause reset - */ -void reset_cpu(ulong addr) -{ - /* request a warm reset */ - writel(RSTMGR_CTRL_SWWARMRSTREQ_LSB, &reset_manager_base->ctrl); - /* - * infinite loop here as watchdog will trigger and reset - * the processor - */ - while (1) - ; -} - -/* - * Release peripherals from reset based on handoff - */ -void reset_deassert_peripherals_handoff(void) -{ - writel(0, &reset_manager_base->per_mod_reset); -} - int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c new file mode 100644 index 0000000..b64db68 --- /dev/null +++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c @@ -0,0 +1,52 @@ +/* + * Copyright Altera Corporation (C) <2013>. All rights reserved + * + * This program is free software; you can redistribute it + * and/or modify it under the terms and conditions of the + * GNU General Public License, version 2, as published by + * the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this program. If not, see + * . + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const struct socfpga_reset_manager *reset_manager_base = + (void *)SOCFPGA_RSTMGR_ADDRESS; + +/* + * Write the reset manager register to cause reset + */ +void reset_cpu(ulong addr) +{ + /* request a warm reset */ + writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB), + &reset_manager_base->ctrl); + /* + * infinite loop here as watchdog will trigger and reset + * the processor + */ + while (1) + ; +} + +/* + * Release peripherals from reset based on handoff + */ +void reset_deassert_peripherals_handoff(void) +{ + writel(0, &reset_manager_base->per_mod_reset); +} + + diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h index d9d2c1c..4930914 100644 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h @@ -22,16 +22,20 @@ void reset_cpu(ulong addr); void reset_deassert_peripherals_handoff(void); struct socfpga_reset_manager { - u32 padding1; + u32 status; u32 ctrl; - u32 padding2; - u32 padding3; + u32 counts; + u32 padding1; u32 mpu_mod_reset; u32 per_mod_reset; u32 per2_mod_reset; u32 brg_mod_reset; }; +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 +#else #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 +#endif #endif /* _RESET_MANAGER_H_ */