Patchwork [v2,07/26] q35: use realize for q35 host

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Submitter Hu Tao
Date July 1, 2013, 10:18 a.m.
Message ID <c3f77354131c2b74417985577a7da73579c7e7fe.1372673778.git.hutao@cn.fujitsu.com>
Download mbox | patch
Permalink /patch/256064/
State New
Headers show

Comments

Hu Tao - July 1, 2013, 10:18 a.m.
and split off memory region initialization into instance_init.

Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
---
 hw/pci-host/q35.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)
Andreas Färber - July 8, 2013, 1:20 a.m.
Am 01.07.2013 12:18, schrieb Hu Tao:
> and split off memory region initialization into instance_init.
> 
> Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
> ---
>  hw/pci-host/q35.c | 29 +++++++++++++++--------------
>  1 file changed, 15 insertions(+), 14 deletions(-)

Thanks, rebased and applied to qom-next:
https://github.com/afaerber/qemu-cpu/commits/qom-next

As mentioned, pci_bus_new() in realize should be replaced with
pci_bus_new_inplace() in instance_init. However investigating that, I
noticed that either function registers VMState, which is supposed to be
done at realize time. This being a system chipset device, I think we can
get away with that (same as for PReP), but I'll do it in a follow-up so
that the blame goes on me.

I think the long-term solution would be extending our realize/unrealize
mechanisms to BusClass.

Regards,
Andreas

Patch

diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 61b525f..244e2f5 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -34,31 +34,27 @@ 
  * Q35 host
  */
 
-static int q35_host_init(SysBusDevice *dev)
+static void q35_host_realize(DeviceState *dev, Error **errp)
 {
     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
+    SysBusDevice *b = SYS_BUS_DEVICE(dev);
 
-    memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
-                          "pci-conf-idx", 4);
-    sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
-    sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
+    sysbus_add_io(b, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
+    sysbus_init_ioports(b, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
 
-    memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
-                          "pci-conf-data", 4);
-    sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
-    sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
+    sysbus_add_io(b, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
+    sysbus_init_ioports(b, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
 
     if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
-        return -1;
+        error_setg(errp, "failed to initialize pcie host");
+        return;
     }
     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
                            s->mch.pci_address_space, s->mch.address_space_io,
                            0, TYPE_PCIE_BUS);
     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
     qdev_init_nofail(DEVICE(&s->mch));
-
-    return 0;
 }
 
 static Property mch_props[] = {
@@ -70,9 +66,8 @@  static Property mch_props[] = {
 static void q35_host_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
-    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
-    k->init = q35_host_init;
+    dc->realize = q35_host_realize;
     dc->props = mch_props;
     dc->fw_name = "pci";
 }
@@ -80,6 +75,12 @@  static void q35_host_class_init(ObjectClass *klass, void *data)
 static void q35_host_initfn(Object *obj)
 {
     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
+    PCIHostState *pci = PCI_HOST_BRIDGE(obj);
+
+    memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
+                          "pci-conf-idx", 4);
+    memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
+                          "pci-conf-data", 4);
 
     object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE);
     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);