From patchwork Sun Jun 30 23:54:47 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Petar Jovanovic X-Patchwork-Id: 255967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3ACE02C02A8 for ; Mon, 1 Jul 2013 09:55:30 +1000 (EST) Received: from localhost ([::1]:33886 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtRSq-0005Qa-Dy for incoming@patchwork.ozlabs.org; Sun, 30 Jun 2013 19:55:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtRSc-0005QV-OY for qemu-devel@nongnu.org; Sun, 30 Jun 2013 19:55:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UtRSb-0007Hp-MF for qemu-devel@nongnu.org; Sun, 30 Jun 2013 19:55:14 -0400 Received: from mail.rt-rk.ftn.uns.ac.rs ([147.91.177.140]:60888 helo=mail.rt-rk.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtRSb-0007He-B0 for qemu-devel@nongnu.org; Sun, 30 Jun 2013 19:55:13 -0400 Received: from mail.rt-rk.com (mail.localdomain [127.0.0.1]) by mail.rt-rk.com (Postfix) with SMTP id 77E5925B485 for ; Mon, 1 Jul 2013 01:55:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com From: Petar Jovanovic To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2013 01:54:47 +0200 Message-Id: <1372636487-124064-1-git-send-email-petar.jovanovic@rt-rk.com> X-Mailer: git-send-email 1.7.9.5 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x X-Received-From: 147.91.177.140 Cc: petar.jovanovic@imgtec.com, aurelien@aurel32.net, rth@twiddle.net Subject: [Qemu-devel] [PATCH v2] target-mips: fix mipsdsp_trunc16_sat16_round X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Petar Jovanovic This change corrects rounding and saturation of Q31 fractional value in mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the corner case for PRECRQ_RS.PH, and this test case is also part of the change. Signed-off-by: Petar Jovanovic Reviewed-by: Richard Henderson --- v2: - added comments to the code target-mips/dsp_helper.c | 16 +++++++++++----- tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c | 24 ++++++++++++++++++++---- 2 files changed, 31 insertions(+), 9 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 4116de9..85950b3 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -648,16 +648,22 @@ static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b, static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a, CPUMIPSState *env) { - int64_t temp; + uint16_t temp; - temp = (int32_t)a + 0x00008000; - if (a > (int)0x7fff8000) { - temp = 0x7FFFFFFF; + /* + * The value 0x00008000 will be added to the input Q31 value, and the code + * needs to check if the addition causes an overflow. Since a positive value + * is added, overflow can happen in one direction only. + */ + if (a > 0x7FFF7FFF) { + temp = 0x7FFF; set_DSPControl_overflow_flag(1, 22, env); + } else { + temp = ((a + 0x8000) >> 16) & 0xFFFF; } - return (temp >> 16) & 0xFFFF; + return temp; } static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a, diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c index 3535b37..da6845b 100644 --- a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c +++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c @@ -12,18 +12,34 @@ int main() result = 0x12348765; __asm - ("precrq_rs.ph.w %0, %1, %2\n\t" + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %1, %2\n\t" : "=r"(rd) : "r"(rs), "r"(rt) ); assert(result == rd); - rs = 0x7fffC678; + rs = 0x7FFFC678; rt = 0x865432A0; - result = 0x7fff8654; + result = 0x7FFF8654; __asm - ("precrq_rs.ph.w %0, %2, %3\n\t" + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(((dsp >> 22) & 0x01) == 1); + assert(result == rd); + + rs = 0xBEEFFEED; + rt = 0x7FFF8000; + result = 0xBEF07FFF; + + __asm + ("wrdsp $0\n\t" + "precrq_rs.ph.w %0, %2, %3\n\t" "rddsp %1\n\t" : "=r"(rd), "=r"(dsp) : "r"(rs), "r"(rt)