From patchwork Sun Jun 30 21:01:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 255926 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3EFCB2C02A6 for ; Mon, 1 Jul 2013 07:04:50 +1000 (EST) Received: from localhost ([::1]:45586 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtOnf-0006c5-Ra for incoming@patchwork.ozlabs.org; Sun, 30 Jun 2013 17:04:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36080) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtOkP-0001Q1-M7 for qemu-devel@nongnu.org; Sun, 30 Jun 2013 17:01:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UtOkN-0003m7-JQ for qemu-devel@nongnu.org; Sun, 30 Jun 2013 17:01:25 -0400 Received: from cantor2.suse.de ([195.135.220.15]:58307 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtOkN-0003lv-7m for qemu-devel@nongnu.org; Sun, 30 Jun 2013 17:01:23 -0400 Received: from relay1.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id AD403A51B7; Sun, 30 Jun 2013 23:01:22 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sun, 30 Jun 2013 23:01:03 +0200 Message-Id: <1372626065-6043-14-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1372626065-6043-1-git-send-email-afaerber@suse.de> References: <1372626065-6043-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [Qemu-devel] [PATCH RFC 13/15] cpu/a15mpcore: Embed GICState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Andreas Färber This covers both emulated and KVM GIC. Prepares for QOM realize. Signed-off-by: Andreas Färber --- hw/cpu/a15mpcore.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 1a15bf8..ee09b57 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -20,6 +20,7 @@ #include "hw/sysbus.h" #include "sysemu/kvm.h" +#include "hw/intc/gic_internal.h" /* A15MP private memory region. */ @@ -35,40 +36,48 @@ typedef struct A15MPPrivState { uint32_t num_cpu; uint32_t num_irq; MemoryRegion container; - DeviceState *gic; + + GICState gic; } A15MPPrivState; static void a15mp_priv_set_irq(void *opaque, int irq, int level) { A15MPPrivState *s = (A15MPPrivState *)opaque; - qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); } static void a15mp_priv_initfn(Object *obj) { SysBusDevice *sbd = SYS_BUS_DEVICE(obj); A15MPPrivState *s = A15MPCORE_PRIV(obj); + DeviceState *gicdev; + const char *gictype = "arm_gic"; + + if (kvm_irqchip_in_kernel()) { + gictype = "kvm-arm-gic"; + } memory_region_init(&s->container, "a15mp-priv-container", 0x8000); sysbus_init_mmio(sbd, &s->container); + + object_initialize(&s->gic, gictype); + gicdev = DEVICE(&s->gic); + qdev_set_parent_bus(gicdev, sysbus_get_default()); + qdev_prop_set_uint32(gicdev, "revision", 2); } static int a15mp_priv_init(SysBusDevice *dev) { A15MPPrivState *s = A15MPCORE_PRIV(dev); + DeviceState *gicdev; SysBusDevice *busdev; - const char *gictype = "arm_gic"; - - if (kvm_irqchip_in_kernel()) { - gictype = "kvm-arm-gic"; - } - s->gic = qdev_create(NULL, gictype); - qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); - qdev_prop_set_uint32(s->gic, "revision", 2); - qdev_init_nofail(s->gic); - busdev = SYS_BUS_DEVICE(s->gic); + gicdev = DEVICE(&s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_init_nofail(gicdev); + busdev = SYS_BUS_DEVICE(&s->gic); /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev);