From patchwork Sat Jun 29 20:01:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 255800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 5B96C2C02B0 for ; Sun, 30 Jun 2013 07:41:52 +1000 (EST) Received: from localhost ([::1]:55035 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ut1Nf-00008g-QY for incoming@patchwork.ozlabs.org; Sat, 29 Jun 2013 16:04:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46012) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ut1Le-0005Re-P3 for qemu-devel@nongnu.org; Sat, 29 Jun 2013 16:02:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ut1Lc-0005Ef-73 for qemu-devel@nongnu.org; Sat, 29 Jun 2013 16:02:18 -0400 Received: from cantor2.suse.de ([195.135.220.15]:57858 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ut1Lb-0005EZ-Ky; Sat, 29 Jun 2013 16:02:16 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 991F5A52BF; Sat, 29 Jun 2013 22:02:14 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Sat, 29 Jun 2013 22:01:17 +0200 Message-Id: <1372536117-28167-2-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.8.1.4 In-Reply-To: <1372536117-28167-1-git-send-email-afaerber@suse.de> References: <1372536117-28167-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4.x X-Received-From: 195.135.220.15 Cc: Peter Maydell , "open list:PowerPC" , Anthony Green , Riku Voipio , Alexander Graf , Blue Swirl , Michael Walle , jan.kiszka@web.de, Paul Brook , "Edgar E. Iglesias" , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Richard Henderson Subject: [Qemu-devel] [PATCH RFC qom-cpu 01/41] log: Change log_cpu_state[_mask]() argument to CPUState X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no longer needed. Add documentation and make the functions available through qemu/log.h outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h was not yet possible due to convoluted include paths, so that some devices grow an implicit and unneeded dependency on qom/cpu.h for now. Signed-off-by: Andreas Färber Reviewed-by: Richard Henderson --- cpu-exec.c | 6 +++--- exec.c | 2 +- include/qemu/log.h | 26 +++++++++++++++++++++----- linux-user/main.c | 5 +++-- target-arm/cpu.c | 2 +- target-cris/cpu.c | 2 +- target-i386/cpu.c | 2 +- target-i386/seg_helper.c | 5 +++-- target-i386/smm_helper.c | 6 ++++-- target-lm32/cpu.c | 2 +- target-lm32/helper.c | 4 ++-- target-m68k/cpu.c | 2 +- target-microblaze/cpu.c | 2 +- target-microblaze/helper.c | 12 ++++++------ target-microblaze/translate.c | 5 ++++- target-mips/cpu.c | 2 +- target-mips/helper.c | 2 +- target-moxie/cpu.c | 2 +- target-openrisc/cpu.c | 2 +- target-openrisc/translate.c | 2 +- target-ppc/mmu-hash32.c | 2 +- target-ppc/mmu-hash64.c | 2 +- target-ppc/mmu_helper.c | 2 +- target-ppc/translate_init.c | 2 +- target-s390x/cpu.c | 2 +- target-sh4/cpu.c | 2 +- target-sh4/helper.c | 2 +- target-sparc/cpu.c | 2 +- target-sparc/int32_helper.c | 2 +- target-sparc/int64_helper.c | 2 +- 30 files changed, 68 insertions(+), 45 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 503b103..9c46846 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -577,15 +577,15 @@ int cpu_exec(CPUArchState *env) if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) { /* restore flags in standard format */ #if defined(TARGET_I386) - log_cpu_state(env, CPU_DUMP_CCOP); + log_cpu_state(cpu, CPU_DUMP_CCOP); #elif defined(TARGET_M68K) cpu_m68k_flush_flags(env, env->cc_op); env->cc_op = CC_OP_FLAGS; env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4); - log_cpu_state(env, 0); + log_cpu_state(cpu, 0); #else - log_cpu_state(env, 0); + log_cpu_state(cpu, 0); #endif } #endif /* DEBUG_DISAS */ diff --git a/exec.c b/exec.c index fe419f7..4e20143 100644 --- a/exec.c +++ b/exec.c @@ -613,7 +613,7 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...) qemu_log("qemu: fatal: "); qemu_log_vprintf(fmt, ap2); qemu_log("\n"); - log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP); + log_cpu_state(cpu, CPU_DUMP_FPU | CPU_DUMP_CCOP); qemu_log_flush(); qemu_log_close(); } diff --git a/include/qemu/log.h b/include/qemu/log.h index a9cf214..d515424 100644 --- a/include/qemu/log.h +++ b/include/qemu/log.h @@ -5,6 +5,7 @@ #include #include #include "qemu/compiler.h" +#include "qom/cpu.h" #ifdef NEED_CPU_H #include "disas/disas.h" #endif @@ -70,22 +71,37 @@ void GCC_FMT_ATTR(2, 3) qemu_log_mask(int mask, const char *fmt, ...); /* Special cases: */ -#ifdef NEED_CPU_H /* cpu_dump_state() logging functions: */ -static inline void log_cpu_state(CPUArchState *env1, int flags) +/** + * log_cpu_state: + * @cpu: The CPU whose state is to be logged. + * @flags: Flags what to log. + * + * Logs the output of cpu_dump_state(). + */ +static inline void log_cpu_state(CPUState *cpu, int flags) { if (qemu_log_enabled()) { - cpu_dump_state(ENV_GET_CPU(env1), qemu_logfile, fprintf, flags); + cpu_dump_state(cpu, qemu_logfile, fprintf, flags); } } -static inline void log_cpu_state_mask(int mask, CPUArchState *env1, int flags) +/** + * log_cpu_state_mask: + * @mask: Mask when to log. + * @cpu: The CPU whose state is to be logged. + * @flags: Flags what to log. + * + * Logs the output of cpu_dump_state() if loglevel includes @mask. + */ +static inline void log_cpu_state_mask(int mask, CPUState *cpu, int flags) { if (qemu_loglevel & mask) { - log_cpu_state(env1, flags); + log_cpu_state(cpu, flags); } } +#ifdef NEED_CPU_H /* disas() and target_disas() to qemu_logfile: */ static inline void log_target_disas(CPUArchState *env, target_ulong start, target_ulong len, int flags) diff --git a/linux-user/main.c b/linux-user/main.c index 67ea9ba..7f15d3d 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1302,11 +1302,12 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) #define EXCP_DUMP(env, fmt, ...) \ do { \ + CPUState *cs = ENV_GET_CPU(env); \ fprintf(stderr, fmt , ## __VA_ARGS__); \ - cpu_dump_state(ENV_GET_CPU(env), stderr, fprintf, 0); \ + cpu_dump_state(cs, stderr, fprintf, 0); \ qemu_log(fmt, ## __VA_ARGS__); \ if (qemu_log_enabled()) { \ - log_cpu_state(env, 0); \ + log_cpu_state(cs, 0); \ } \ } while (0) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 1bc227e..84974a9 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -65,7 +65,7 @@ static void arm_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } acc->parent_reset(s); diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 6a3bdf0..f6c4f3f 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -36,7 +36,7 @@ static void cris_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } ccc->parent_reset(s); diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b7416fe..82a451b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2177,7 +2177,7 @@ static void x86_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP); + log_cpu_state(s, CPU_DUMP_FPU | CPU_DUMP_CCOP); } xcc->parent_reset(s); diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 9c799e1..42ee823 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -31,7 +31,7 @@ #ifdef DEBUG_PCALL # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__) # define LOG_PCALL_STATE(env) \ - log_cpu_state_mask(CPU_LOG_PCALL, (env), CPU_DUMP_CCOP) + log_cpu_state_mask(CPU_LOG_PCALL, CPU(x86_env_get_cpu(env)), CPU_DUMP_CCOP) #else # define LOG_PCALL(...) do { } while (0) # define LOG_PCALL_STATE(env) do { } while (0) @@ -1165,6 +1165,7 @@ static void do_interrupt_all(CPUX86State *env, int intno, int is_int, { if (qemu_loglevel_mask(CPU_LOG_INT)) { if ((env->cr[0] & CR0_PE_MASK)) { + X86CPU *cpu = x86_env_get_cpu(env); static int count; qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx @@ -1180,7 +1181,7 @@ static void do_interrupt_all(CPUX86State *env, int intno, int is_int, qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]); } qemu_log("\n"); - log_cpu_state(env, CPU_DUMP_CCOP); + log_cpu_state(CPU(cpu), CPU_DUMP_CCOP); #if 0 { int i; diff --git a/target-i386/smm_helper.c b/target-i386/smm_helper.c index 2489573..5abdfc8 100644 --- a/target-i386/smm_helper.c +++ b/target-i386/smm_helper.c @@ -42,12 +42,13 @@ void helper_rsm(CPUX86State *env) void do_smm_enter(CPUX86State *env) { + X86CPU *cpu = x86_env_get_cpu(env); target_ulong sm_state; SegmentCache *dt; int i, offset; qemu_log_mask(CPU_LOG_INT, "SMM: enter\n"); - log_cpu_state_mask(CPU_LOG_INT, env, CPU_DUMP_CCOP); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); env->hflags |= HF_SMM_MASK; cpu_smm_update(env); @@ -179,6 +180,7 @@ void do_smm_enter(CPUX86State *env) void helper_rsm(CPUX86State *env) { + X86CPU *cpu = x86_env_get_cpu(env); target_ulong sm_state; int i, offset; uint32_t val; @@ -295,7 +297,7 @@ void helper_rsm(CPUX86State *env) cpu_smm_update(env); qemu_log_mask(CPU_LOG_INT, "SMM: after RSM\n"); - log_cpu_state_mask(CPU_LOG_INT, env, CPU_DUMP_CCOP); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), CPU_DUMP_CCOP); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 02f8436..6e44d45 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -31,7 +31,7 @@ static void lm32_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } lcc->parent_reset(s); diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 03fa5fb..615b44e 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -70,7 +70,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) } else { env->pc = env->eba + (env->exception_index * 32); } - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; case EXCP_BREAKPOINT: case EXCP_WATCHPOINT: @@ -79,7 +79,7 @@ void lm32_cpu_do_interrupt(CPUState *cs) env->ie |= (env->ie & IE_IE) ? IE_BIE : 0; env->ie &= ~IE_IE; env->pc = env->deba + (env->exception_index * 32); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, cs, 0); break; default: cpu_abort(env, "unhandled exception type=%d\n", diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index 799869f..c9ac30f 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -37,7 +37,7 @@ static void m68k_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index a0fcdf4..d93519e 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -35,7 +35,7 @@ static void mb_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 01d4bbf..86aad6a 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "hw exception at pc=%x ear=%x esr=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->sregs[SR_ESR], env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; @@ -175,7 +175,7 @@ void mb_cpu_do_interrupt(CPUState *cs) "bimm exception at pc=%x iflags=%x\n", env->sregs[SR_PC], env->iflags); env->regs[17] -= 4; - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); } } else if (env->iflags & IMM_FLAG) { D(qemu_log("IMM_FLAG set at exception\n")); @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "exception at pc=%x ear=%x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); env->iflags &= ~(IMM_FLAG | D_FLAG); env->sregs[SR_PC] = cpu->base_vectors + 0x20; break; @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags, sym); - log_cpu_state(env, 0); + log_cpu_state(CPU(cpu), 0); } } #endif @@ -236,7 +236,7 @@ void mb_cpu_do_interrupt(CPUState *cs) env->regs[14] = env->sregs[SR_PC]; env->sregs[SR_PC] = cpu->base_vectors + 0x10; - //log_cpu_state_mask(CPU_LOG_INT, env, 0); + //log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); break; case EXCP_BREAK: @@ -247,7 +247,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "break at pc=%x msr=%x %x iflags=%x\n", env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags); - log_cpu_state_mask(CPU_LOG_INT, env, 0); + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); env->sregs[SR_MSR] |= t; env->sregs[SR_MSR] |= MSR_BIP; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 54f439f..f9acdb1 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1741,6 +1741,9 @@ static void gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, int search_pc) { +#if !SIM_COMPAT + MicroBlazeCPU *cpu = mb_env_get_cpu(env); +#endif uint16_t *gen_opc_end; uint32_t pc_start; int j, lj; @@ -1776,7 +1779,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { #if !SIM_COMPAT qemu_log("--------------\n"); - log_cpu_state(env, 0); + log_cpu_state(CPU(cpu), 0); #endif } diff --git a/target-mips/cpu.c b/target-mips/cpu.c index b61e207..cab9572 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -31,7 +31,7 @@ static void mips_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-mips/helper.c b/target-mips/helper.c index 36929dd..6983b92 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -276,7 +276,7 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw, int ret = 0; #if 0 - log_cpu_state(env, 0); + log_cpu_state(CPU(mips_env_get_cpu(env)), 0); #endif qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n", __func__, env->active_tc.PC, address, rw, mmu_idx); diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index f3c0d22..7314d4b 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c @@ -30,7 +30,7 @@ static void moxie_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } mcc->parent_reset(s); diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index fd90d37..cab5b52 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -28,7 +28,7 @@ static void openrisc_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(&cpu->env, 0); + log_cpu_state(s, 0); } occ->parent_reset(s); diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index c59fd02..f222834 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1684,7 +1684,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, dc->singlestep_enabled = cpu->env.singlestep_enabled; if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("-----------------------------------------\n"); - log_cpu_state(&cpu->env, 0); + log_cpu_state(CPU(cpu), 0); } next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c index f6adf22..b5ebe07 100644 --- a/target-ppc/mmu-hash32.c +++ b/target-ppc/mmu-hash32.c @@ -29,7 +29,7 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(env) log_cpu_state(CPU(ppc_env_get_cpu(env)), 0) #else # define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(...) do { } while (0) diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c index 5c67ec3..759cef3 100644 --- a/target-ppc/mmu-hash64.c +++ b/target-ppc/mmu-hash64.c @@ -28,7 +28,7 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(env) log_cpu_state(CPU(ppc_env_get_cpu(env)), 0) #else # define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(...) do { } while (0) diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 53deba5..26f513f 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -32,7 +32,7 @@ #ifdef DEBUG_MMU # define LOG_MMU(...) qemu_log(__VA_ARGS__) -# define LOG_MMU_STATE(env) log_cpu_state((env), 0) +# define LOG_MMU_STATE(env) log_cpu_state(CPU(ppc_env_get_cpu(env)), 0) #else # define LOG_MMU(...) do { } while (0) # define LOG_MMU_STATE(...) do { } while (0) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index fa5e09f..3700a1a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -8188,7 +8188,7 @@ static void ppc_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } pcc->parent_reset(s); diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index c3697cd..732d393 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -67,7 +67,7 @@ static void s390_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } s390_del_running_cpu(cpu); diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index e739156..653acec 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -33,7 +33,7 @@ static void superh_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } scc->parent_reset(s); diff --git a/target-sh4/helper.c b/target-sh4/helper.c index ce10ca8..cb6a2d2 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -159,7 +159,7 @@ void superh_cpu_do_interrupt(CPUState *cs) } qemu_log("exception 0x%03x [%s] raised\n", irq_vector, expname); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); } env->ssr = env->sr; diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 65ae6f7..4cbb206 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -32,7 +32,7 @@ static void sparc_cpu_reset(CPUState *s) if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(env, 0); + log_cpu_state(s, 0); } scc->parent_reset(s); diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c index 7221460..d532238 100644 --- a/target-sparc/int32_helper.c +++ b/target-sparc/int32_helper.c @@ -86,7 +86,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) } qemu_log("%6d: %s (v=%02x)\n", count, name, intno); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); #if 0 { int i; diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c index f411884..bf7dd86 100644 --- a/target-sparc/int64_helper.c +++ b/target-sparc/int64_helper.c @@ -92,7 +92,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) } qemu_log("%6d: %s (v=%04x)\n", count, name, intno); - log_cpu_state(env, 0); + log_cpu_state(cs, 0); #if 0 { int i;