Patchwork [RFC,qom-cpu,40/41] gdbstub: Move num_g_regs to CPUState and NUM_CORE_REGS to CPUClass

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Submitter Andreas Färber
Date June 29, 2013, 8:01 p.m.
Message ID <1372536117-28167-41-git-send-email-afaerber@suse.de>
Download mbox | patch
Permalink /patch/255798/
State New
Headers show

Comments

Andreas Färber - June 29, 2013, 8:01 p.m.
As a side effect this should fix coprocessor register numbering for SMP.

Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 gdbstub.c                   | 80 ++++++++++-----------------------------------
 include/qom/cpu.h           |  3 ++
 qom/cpu.c                   |  9 +++++
 target-alpha/cpu.c          |  1 +
 target-arm/cpu.c            |  1 +
 target-cris/cpu.c           |  2 ++
 target-i386/cpu.c           |  1 +
 target-lm32/cpu.c           |  1 +
 target-m68k/cpu.c           |  1 +
 target-microblaze/cpu.c     |  1 +
 target-mips/cpu.c           |  2 ++
 target-openrisc/cpu.c       |  1 +
 target-ppc/translate_init.c |  2 ++
 target-s390x/cpu.c          |  1 +
 target-sh4/cpu.c            |  1 +
 target-sparc/cpu.c          |  6 ++++
 target-xtensa/cpu.c         |  3 ++
 target-xtensa/helper.c      |  8 +++++
 18 files changed, 61 insertions(+), 63 deletions(-)

Patch

diff --git a/gdbstub.c b/gdbstub.c
index d08cfd3..1a827c2 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -530,8 +530,6 @@  static const int gpr_map[16] = {
 #endif
 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 
-#define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
-
 #define IDX_IP_REG      CPU_NB_REGS
 #define IDX_FLAGS_REG   (IDX_IP_REG + 1)
 #define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
@@ -702,7 +700,6 @@  static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n)
    historical mishap the FP registers appear in between core integer
    regs and PC, MSR, CR, and so forth.  We hack round this by giving the
    FP regs zero size when talking to a newer gdb.  */
-#define NUM_CORE_REGS 71
 #if defined (TARGET_PPC64)
 #define GDB_CORE_XML "power64-core.xml"
 #else
@@ -796,12 +793,6 @@  static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n)
 
 #elif defined (TARGET_SPARC)
 
-#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
-#define NUM_CORE_REGS 86
-#else
-#define NUM_CORE_REGS 72
-#endif
-
 #ifdef TARGET_ABI32
 #define GET_REGA(val) GET_REG32(val)
 #else
@@ -948,7 +939,6 @@  static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n)
    the FPA registers appear in between core integer regs and the CPSR.
    We hack round this by giving the FPA regs zero size when talking to a
    newer gdb.  */
-#define NUM_CORE_REGS 26
 #define GDB_CORE_XML "arm-core.xml"
 
 static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n)
@@ -1017,8 +1007,6 @@  static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n)
 
 #elif defined (TARGET_M68K)
 
-#define NUM_CORE_REGS 18
-
 #define GDB_CORE_XML "cf-core.xml"
 
 static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n)
@@ -1063,8 +1051,6 @@  static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_MIPS)
 
-#define NUM_CORE_REGS 73
-
 static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
@@ -1165,8 +1151,6 @@  static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n)
 }
 #elif defined(TARGET_OPENRISC)
 
-#define NUM_CORE_REGS (32 + 3)
-
 static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
@@ -1195,9 +1179,10 @@  static int cpu_gdb_read_register(CPUOpenRISCState *env, uint8_t *mem_buf, int n)
 static int cpu_gdb_write_register(CPUOpenRISCState *env,
                                   uint8_t *mem_buf, int n)
 {
+    CPUClass *cc = CPU_GET_CLASS(openrisc_env_get_cpu(env));
     uint32_t tmp;
 
-    if (n > NUM_CORE_REGS) {
+    if (n > cc->gdb_num_core_regs) {
         return 0;
     }
 
@@ -1230,8 +1215,6 @@  static int cpu_gdb_write_register(CPUOpenRISCState *env,
 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
 /* FIXME: We should use XML for this.  */
 
-#define NUM_CORE_REGS 59
-
 static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n)
 {
     switch (n) {
@@ -1347,8 +1330,6 @@  static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_MICROBLAZE)
 
-#define NUM_CORE_REGS (32 + 5)
-
 static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
 {
     if (n < 32) {
@@ -1361,10 +1342,12 @@  static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n)
 
 static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
 {
+    CPUClass *cc = CPU_GET_CLASS(mb_env_get_cpu(env));
     uint32_t tmp;
 
-    if (n > NUM_CORE_REGS)
+    if (n > cc->gdb_num_core_regs) {
 	return 0;
+    }
 
     tmp = ldl_p(mem_buf);
 
@@ -1377,8 +1360,6 @@  static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_CRIS)
 
-#define NUM_CORE_REGS 49
-
 static int
 read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n)
 {
@@ -1473,8 +1454,6 @@  static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_ALPHA)
 
-#define NUM_CORE_REGS 67
-
 static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
 {
     uint64_t val;
@@ -1543,8 +1522,6 @@  static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n)
 }
 #elif defined (TARGET_S390X)
 
-#define NUM_CORE_REGS  S390_NUM_REGS
-
 static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n)
 {
     uint64_t val;
@@ -1614,7 +1591,6 @@  static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n)
 #elif defined (TARGET_LM32)
 
 #include "hw/lm32/lm32_pic.h"
-#define NUM_CORE_REGS (32 + 7)
 
 static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
 {
@@ -1651,9 +1627,10 @@  static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n)
 
 static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
 {
+    CPUClass *cc = CPU_GET_CLASS(lm32_env_get_cpu(env));
     uint32_t tmp;
 
-    if (n > NUM_CORE_REGS) {
+    if (n > cc->gdb_num_core_regs) {
         return 0;
     }
 
@@ -1687,15 +1664,6 @@  static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n)
 }
 #elif defined(TARGET_XTENSA)
 
-/* Use num_core_regs to see only non-privileged registers in an unmodified gdb.
- * Use num_regs to see all registers. gdb modification is required for that:
- * reset bit 0 in the 'flags' field of the registers definitions in the
- * gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
- */
-#define NUM_CORE_REGS \
-  (XTENSA_CPU_GET_CLASS(xtensa_env_get_cpu(env))->config->gdb_regmap.num_regs)
-#define num_g_regs NUM_CORE_REGS
-
 static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
 {
     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(xtensa_env_get_cpu(env));
@@ -1786,8 +1754,6 @@  static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n)
 }
 #else
 
-#define NUM_CORE_REGS 0
-
 static int cpu_gdb_read_register(CPUArchState *env, uint8_t *mem_buf, int n)
 {
     return 0;
@@ -1800,10 +1766,6 @@  static int cpu_gdb_write_register(CPUArchState *env, uint8_t *mem_buf, int n)
 
 #endif
 
-#if !defined(TARGET_XTENSA)
-static int num_g_regs = NUM_CORE_REGS;
-#endif
-
 #ifdef GDB_CORE_XML
 /* Encode data using the encoding for 'x' packets.  */
 static int memtox(char *buf, const char *mem, int len)
@@ -1872,11 +1834,13 @@  static const char *get_feature_xml(const char *p, const char **newp)
 
 static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
 {
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     CPUArchState *env = cpu->env_ptr;
     GDBRegisterState *r;
 
-    if (reg < NUM_CORE_REGS)
+    if (reg < cc->gdb_num_core_regs) {
         return cpu_gdb_read_register(env, mem_buf, reg);
+    }
 
     for (r = cpu->gdb_regs; r; r = r->next) {
         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
@@ -1888,11 +1852,13 @@  static int gdb_read_register(CPUState *cpu, uint8_t *mem_buf, int reg)
 
 static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)
 {
+    CPUClass *cc = CPU_GET_CLASS(cpu);
     CPUArchState *env = cpu->env_ptr;
     GDBRegisterState *r;
 
-    if (reg < NUM_CORE_REGS)
+    if (reg < cc->gdb_num_core_regs) {
         return cpu_gdb_write_register(env, mem_buf, reg);
+    }
 
     for (r = cpu->gdb_regs; r; r = r->next) {
         if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
@@ -1915,7 +1881,6 @@  void gdb_register_coprocessor(CPUState *cpu,
 {
     GDBRegisterState *s;
     GDBRegisterState **p;
-    static int last_reg = NUM_CORE_REGS;
 
     p = &cpu->gdb_regs;
     while (*p) {
@@ -1926,21 +1891,19 @@  void gdb_register_coprocessor(CPUState *cpu,
     }
 
     s = g_new0(GDBRegisterState, 1);
-    s->base_reg = last_reg;
+    s->base_reg = cpu->gdb_num_regs;
     s->num_regs = num_regs;
     s->get_reg = get_reg;
     s->set_reg = set_reg;
     s->xml = xml;
 
     /* Add to end of list.  */
-    last_reg += num_regs;
+    cpu->gdb_num_regs += num_regs;
     *p = s;
     if (g_pos) {
         if (g_pos != s->base_reg) {
             fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
                     "Expected %d got %d\n", xml, g_pos, s->base_reg);
-        } else {
-            num_g_regs = last_reg;
         }
     }
 }
@@ -2061,9 +2024,6 @@  static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
 
 static int gdb_handle_packet(GDBState *s, const char *line_buf)
 {
-#ifdef TARGET_XTENSA
-    CPUArchState *env;
-#endif
     CPUState *cpu;
     const char *p;
     uint32_t thread;
@@ -2211,11 +2171,8 @@  static int gdb_handle_packet(GDBState *s, const char *line_buf)
         break;
     case 'g':
         cpu_synchronize_state(s->g_cpu);
-#ifdef TARGET_XTENSA
-        env = s->g_cpu->env_ptr;
-#endif
         len = 0;
-        for (addr = 0; addr < num_g_regs; addr++) {
+        for (addr = 0; addr < s->g_cpu->gdb_num_regs; addr++) {
             reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
             len += reg_size;
         }
@@ -2224,13 +2181,10 @@  static int gdb_handle_packet(GDBState *s, const char *line_buf)
         break;
     case 'G':
         cpu_synchronize_state(s->g_cpu);
-#ifdef TARGET_XTENSA
-        env = s->g_cpu->env_ptr;
-#endif
         registers = mem_buf;
         len = strlen(p) / 2;
         hextomem((uint8_t *)registers, p, len);
-        for (addr = 0; addr < num_g_regs && len > 0; addr++) {
+        for (addr = 0; addr < s->g_cpu->gdb_num_regs && len > 0; addr++) {
             reg_size = gdb_write_register(s->g_cpu, registers, addr);
             len -= reg_size;
             registers += reg_size;
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 78fbdac..f89c49e 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -100,6 +100,8 @@  typedef struct CPUClass {
                             int cpuid, void *opaque);
     int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
                                 void *opaque);
+
+    int gdb_num_core_regs;
 } CPUClass;
 
 struct KVMState;
@@ -157,6 +159,7 @@  struct CPUState {
     void *env_ptr; /* CPUArchState */
     struct TranslationBlock *current_tb;
     struct GDBRegisterState *gdb_regs;
+    int gdb_num_regs;
     CPUState *next_cpu;
 
     int kvm_fd;
diff --git a/qom/cpu.c b/qom/cpu.c
index 5c45ab5..2839ddf 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -226,6 +226,14 @@  static void cpu_common_realizefn(DeviceState *dev, Error **errp)
     }
 }
 
+static void cpu_common_initfn(Object *obj)
+{
+    CPUState *cpu = CPU(obj);
+    CPUClass *cc = CPU_GET_CLASS(obj);
+
+    cpu->gdb_num_regs = cc->gdb_num_core_regs;
+}
+
 static int64_t cpu_common_get_arch_id(CPUState *cpu)
 {
     return cpu->cpu_index;
@@ -253,6 +261,7 @@  static const TypeInfo cpu_type_info = {
     .name = TYPE_CPU,
     .parent = TYPE_DEVICE,
     .instance_size = sizeof(CPUState),
+    .instance_init = cpu_common_initfn,
     .abstract = true,
     .class_size = sizeof(CPUClass),
     .class_init = cpu_class_init,
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index e03e74b..028cec1 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -276,6 +276,7 @@  static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
     dc->vmsd = &vmstate_alpha_cpu;
 #endif
+    cc->gdb_num_core_regs = 67;
 }
 
 static const TypeInfo alpha_cpu_type_info = {
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 5f8a8f9..e04bcc3 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -823,6 +823,7 @@  static void arm_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_arm_cpu;
 #endif
+    cc->gdb_num_core_regs = 26;
 }
 
 static void cpu_register(const ARMCPUInfo *info)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 4d45b98..426a321 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -258,6 +258,8 @@  static void cris_cpu_class_init(ObjectClass *oc, void *data)
 #ifndef CONFIG_USER_ONLY
     cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
 #endif
+
+    cc->gdb_num_core_regs = 49;
 }
 
 static const TypeInfo cris_cpu_type_info = {
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 6b1205d..7c6f1d3 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2549,6 +2549,7 @@  static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
     cc->vmsd = &vmstate_x86_cpu;
 #endif
+    cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
 }
 
 static const TypeInfo x86_cpu_type_info = {
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 705dd55..ec5f0e0 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -91,6 +91,7 @@  static void lm32_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
     cc->vmsd = &vmstate_lm32_cpu;
 #endif
+    cc->gdb_num_core_regs = 32 + 7;
 }
 
 static const TypeInfo lm32_cpu_type_info = {
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 5328fda..35c203c 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -194,6 +194,7 @@  static void m68k_cpu_class_init(ObjectClass *c, void *data)
     cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
 #endif
     dc->vmsd = &vmstate_m68k_cpu;
+    cc->gdb_num_core_regs = 18;
 }
 
 static void register_cpu_type(const M68kCPUInfo *info)
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 90cc088..f2e538a 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -147,6 +147,7 @@  static void mb_cpu_class_init(ObjectClass *oc, void *data)
 #endif
     dc->vmsd = &vmstate_mb_cpu;
     dc->props = mb_properties;
+    cc->gdb_num_core_regs = 32 + 5;
 }
 
 static const TypeInfo mb_cpu_type_info = {
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 10f6f69..17d49b8 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -104,6 +104,8 @@  static void mips_cpu_class_init(ObjectClass *c, void *data)
     cc->do_unassigned_access = mips_cpu_unassigned_access;
     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 #endif
+
+    cc->gdb_num_core_regs = 73;
 }
 
 static const TypeInfo mips_cpu_type_info = {
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 2b7a40e..a2cd4be 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -156,6 +156,7 @@  static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
     dc->vmsd = &vmstate_openrisc_cpu;
 #endif
+    cc->gdb_num_core_regs = 32 + 3;
 }
 
 static void cpu_register(const OpenRISCCPUInfo *info)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 24821f9..e1d9d02 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8313,6 +8313,8 @@  static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     cc->dump_state = ppc_cpu_dump_state;
     cc->dump_statistics = ppc_cpu_dump_statistics;
     cc->set_pc = ppc_cpu_set_pc;
+
+    cc->gdb_num_core_regs = 71;
 }
 
 static const TypeInfo ppc_cpu_type_info = {
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index ea29f9c..ae62143 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -177,6 +177,7 @@  static void s390_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
 #endif
     dc->vmsd = &vmstate_s390_cpu;
+    cc->gdb_num_core_regs = S390_NUM_REGS;
 }
 
 static const TypeInfo s390_cpu_type_info = {
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index c9d6590..7f5c47a 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -290,6 +290,7 @@  static void superh_cpu_class_init(ObjectClass *oc, void *data)
     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 #endif
     dc->vmsd = &vmstate_sh_cpu;
+    cc->gdb_num_core_regs = 59;
 }
 
 static const TypeInfo superh_cpu_type_info = {
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index bd9d216..b35f2d1 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -791,6 +791,12 @@  static void sparc_cpu_class_init(ObjectClass *oc, void *data)
     cc->do_unassigned_access = sparc_cpu_unassigned_access;
     cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
 #endif
+
+#if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
+    cc->gdb_num_core_regs = 86;
+#else
+    cc->gdb_num_core_regs = 72;
+#endif
 }
 
 static const TypeInfo sparc_cpu_type_info = {
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 75762ad..eaafacf 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -85,8 +85,11 @@  static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
 
 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
 {
+    CPUState *cs = CPU(dev);
     XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
 
+    cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
+
     xcc->parent_realize(dev, errp);
 }
 
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index a1e524d..29f4db6 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -37,10 +37,18 @@  static struct XtensaConfigList *xtensa_cores;
 
 static void xtensa_core_class_init(ObjectClass *oc, void *data)
 {
+    CPUClass *cc = CPU_CLASS(oc);
     XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
     const XtensaConfig *config = data;
 
     xcc->config = config;
+
+    /* Use num_core_regs to see only non-privileged registers in an unmodified
+     * gdb. Use num_regs to see all registers. gdb modification is required
+     * for that: reset bit 0 in the 'flags' field of the registers definitions
+     * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay.
+     */
+    cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
 }
 
 void xtensa_register_core(XtensaConfigList *node)